llvm-6502/test/MC/ARM/udf-arm-diagnostics.s

@ RUN: not llvm-mc -triple arm-eabi %s 2>&1 | FileCheck %s

	.syntax unified
	.text
	.arm

undefined:
	udfpl

@ CHECK: error: instruction 'udf' is not predicable, but condition code specified
@ CHECK: 	udfpl
@ CHECK: 	^

	udf #65536

@ CHECK: error: invalid operand for instruction
@ CHECK: 	udf #65536
@ CHECK: 	    ^
ARM: implement support for the UDF mnemonic The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208751 91177308-0d34-0410-b5e6-96231b3b80d8 2014-05-14 03:47:39 +00:00			`@ RUN: not llvm-mc -triple arm-eabi %s 2>&1 \| FileCheck %s`

			`.syntax unified`
			`.text`
			`.arm`

			`undefined:`
			`udfpl`

			`@ CHECK: error: instruction 'udf' is not predicable, but condition code specified`
			`@ CHECK: udfpl`
			`@ CHECK: ^`

			`udf #65536`

			`@ CHECK: error: invalid operand for instruction`
			`@ CHECK: udf #65536`
			`@ CHECK: ^`