2014-04-03 16:01:44 +00:00
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; RUN: llc -mtriple=arm-eabi -mattr=+neon -print-before=post-RA-sched %s -o - 2>&1 \
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; RUN: | FileCheck %s
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PR 18466: Fix ARM Pseudo Expansion
When expanding neon pseudo stores, it may miss the implicit uses of sub
regs, which may cause post RA scheduler reorder instructions that
breakes anti dependency.
For example:
VST1d64QPseudo %R0<kill>, 16, %Q9_Q10, pred:14, pred:%noreg
will be expanded to
VST1d64Q %R0<kill>, 16, %D18, pred:14, pred:%noreg;
An instruction that defines %D20 may be scheduled before the store by
mistake.
This patches adds implicit uses for such case. For the example above, it
emits:
VST1d64Q %R0<kill>, 8, %D18, pred:14, pred:%noreg, %Q9_Q10<imp-use>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199282 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 01:32:12 +00:00
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define void @vst(i8* %m, [4 x i64] %v) {
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entry:
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; CHECK: vst:
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; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
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%v0 = extractvalue [4 x i64] %v, 0
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%v1 = extractvalue [4 x i64] %v, 1
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%v2 = extractvalue [4 x i64] %v, 2
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%v3 = extractvalue [4 x i64] %v, 3
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%t0 = bitcast i64 %v0 to <8 x i8>
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%t1 = bitcast i64 %v1 to <8 x i8>
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%t2 = bitcast i64 %v2 to <8 x i8>
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%t3 = bitcast i64 %v3 to <8 x i8>
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%s0 = bitcast <8 x i8> %t0 to <1 x i64>
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%s1 = bitcast <8 x i8> %t1 to <1 x i64>
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%s2 = bitcast <8 x i8> %t2 to <1 x i64>
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%s3 = bitcast <8 x i8> %t3 to <1 x i64>
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%tmp0 = bitcast <1 x i64> %s2 to i64
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%tmp1 = bitcast <1 x i64> %s3 to i64
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%n0 = insertelement <2 x i64> undef, i64 %tmp0, i32 0
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%n1 = insertelement <2 x i64> %n0, i64 %tmp1, i32 1
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call void @llvm.arm.neon.vst4.v1i64(i8* %m, <1 x i64> %s0, <1 x i64> %s1, <1 x i64> %s2, <1 x i64> %s3, i32 8)
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call void @bar(<2 x i64> %n1)
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ret void
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}
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
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; CHECK: vtbx4:
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; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x4_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
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%tmp7 = load <8 x i8>* %C
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%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
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call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8)
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ret <8 x i8> %tmp8
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}
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declare void @llvm.arm.neon.vst4.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32)
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declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare void @bar2(%struct.__neon_int8x8x4_t, <8 x i8>)
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declare void @bar(<2 x i64> %arg)
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