llvm-6502/test/CodeGen/X86/widen_extract-1.ll

; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; widen extract subvector

define void @convert(<2 x double>* %dst.addr, <3 x double> %src)  {
entry:
; CHECK: convert:
; CHECK: unpcklpd {{%xmm[0-7]}}, {{%xmm[0-7]}}
; CHECK-NEXT: movapd
  %val = shufflevector <3 x double> %src, <3 x double> undef, <2 x i32> < i32 0, i32 1>
  store <2 x double> %val, <2 x double>* %dst.addr
  ret void
}
now that generic vector types aren't selected onto MMX registers, these tests don't need -disable-mmx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122188 91177308-0d34-0410-b5e6-96231b3b80d8 2010-12-19 20:12:58 +00:00			`; RUN: llc < %s -march=x86-64 -mattr=+sse42 \| FileCheck %s`
Add test case for r84279 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84280 91177308-0d34-0410-b5e6-96231b3b80d8 2009-10-16 22:07:19 +00:00			`; widen extract subvector`

			`define void @convert(<2 x double>* %dst.addr, <3 x double> %src) {`
			`entry:`
			`; CHECK: convert:`
			`; CHECK: unpcklpd {{%xmm[0-7]}}, {{%xmm[0-7]}}`
			`; CHECK-NEXT: movapd`
			`%val = shufflevector <3 x double> %src, <3 x double> undef, <2 x i32> < i32 0, i32 1>`
			`store <2 x double> %val, <2 x double>* %dst.addr`
			`ret void`
			`}`