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llvm-6502/test/Analysis/ScalarEvolution/sext-iv-1.ll

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Change tests from "opt %s" to "opt < %s" so that opt doesn't see the input filename so that opt doesn't print the input filename in the output so that grep lines in the tests don't unintentionally match strings in the input filename. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81537 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11 18:01:28 +00:00
; RUN: opt < %s -disable-output -scalar-evolution -analyze \
Use WriteAsOperand instead of getName() to print loop header names, so that unnamed blocks are handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-09 18:17:45 +00:00
; RUN: | grep { --> (sext i. \{.\*,+,.\*\}<%bb1> to i64)} | count 5
Generalize the cast-of-addrec folding to handle folding of SCEVs like (sext i8 {-128,+,1} to i64) to i64 {-128,+,1}, where the iteration crosses from negative to positive, but is still safe if the trip count is within range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70421 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 22:28:28 +00:00
; Don't convert (sext {...,+,...}) to {sext(...),+,sext(...)} in cases
; where the trip count is not within range.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
define void @foo0(double* nocapture %x) nounwind {
bb1.thread:
br label %bb1
bb1: ; preds = %bb1, %bb1.thread
%i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ] ; <i64> [#uses=3]
%0 = trunc i64 %i.0.reg2mem.0 to i7 ; <i8> [#uses=1]
%1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
%2 = sext i9 %1 to i64 ; <i64> [#uses=1]
%3 = getelementptr double* %x, i64 %2 ; <double*> [#uses=1]
%4 = load double* %3, align 8 ; <double> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
%5 = fmul double %4, 3.900000e+00 ; <double> [#uses=1]
Generalize the cast-of-addrec folding to handle folding of SCEVs like (sext i8 {-128,+,1} to i64) to i64 {-128,+,1}, where the iteration crosses from negative to positive, but is still safe if the trip count is within range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70421 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 22:28:28 +00:00
%6 = sext i7 %0 to i64 ; <i64> [#uses=1]
%7 = getelementptr double* %x, i64 %6 ; <double*> [#uses=1]
store double %5, double* %7, align 8
%8 = add i64 %i.0.reg2mem.0, 1 ; <i64> [#uses=2]
%9 = icmp sgt i64 %8, 127 ; <i1> [#uses=1]
br i1 %9, label %return, label %bb1
return: ; preds = %bb1
ret void
}
define void @foo1(double* nocapture %x) nounwind {
bb1.thread:
br label %bb1
bb1: ; preds = %bb1, %bb1.thread
%i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ] ; <i64> [#uses=3]
%0 = trunc i64 %i.0.reg2mem.0 to i8 ; <i8> [#uses=1]
%1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
%2 = sext i9 %1 to i64 ; <i64> [#uses=1]
%3 = getelementptr double* %x, i64 %2 ; <double*> [#uses=1]
%4 = load double* %3, align 8 ; <double> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
%5 = fmul double %4, 3.900000e+00 ; <double> [#uses=1]
Generalize the cast-of-addrec folding to handle folding of SCEVs like (sext i8 {-128,+,1} to i64) to i64 {-128,+,1}, where the iteration crosses from negative to positive, but is still safe if the trip count is within range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70421 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 22:28:28 +00:00
%6 = sext i8 %0 to i64 ; <i64> [#uses=1]
%7 = getelementptr double* %x, i64 %6 ; <double*> [#uses=1]
store double %5, double* %7, align 8
%8 = add i64 %i.0.reg2mem.0, 1 ; <i64> [#uses=2]
%9 = icmp sgt i64 %8, 128 ; <i1> [#uses=1]
br i1 %9, label %return, label %bb1
return: ; preds = %bb1
ret void
}
define void @foo2(double* nocapture %x) nounwind {
bb1.thread:
br label %bb1
bb1: ; preds = %bb1, %bb1.thread
%i.0.reg2mem.0 = phi i64 [ -129, %bb1.thread ], [ %8, %bb1 ] ; <i64> [#uses=3]
%0 = trunc i64 %i.0.reg2mem.0 to i8 ; <i8> [#uses=1]
%1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
%2 = sext i9 %1 to i64 ; <i64> [#uses=1]
%3 = getelementptr double* %x, i64 %2 ; <double*> [#uses=1]
%4 = load double* %3, align 8 ; <double> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
%5 = fmul double %4, 3.900000e+00 ; <double> [#uses=1]
Generalize the cast-of-addrec folding to handle folding of SCEVs like (sext i8 {-128,+,1} to i64) to i64 {-128,+,1}, where the iteration crosses from negative to positive, but is still safe if the trip count is within range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70421 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 22:28:28 +00:00
%6 = sext i8 %0 to i64 ; <i64> [#uses=1]
%7 = getelementptr double* %x, i64 %6 ; <double*> [#uses=1]
store double %5, double* %7, align 8
%8 = add i64 %i.0.reg2mem.0, 1 ; <i64> [#uses=2]
%9 = icmp sgt i64 %8, 127 ; <i1> [#uses=1]
br i1 %9, label %return, label %bb1
return: ; preds = %bb1
ret void
}
define void @foo3(double* nocapture %x) nounwind {
bb1.thread:
br label %bb1
bb1: ; preds = %bb1, %bb1.thread
%i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ] ; <i64> [#uses=3]
%0 = trunc i64 %i.0.reg2mem.0 to i8 ; <i8> [#uses=1]
%1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
%2 = sext i9 %1 to i64 ; <i64> [#uses=1]
%3 = getelementptr double* %x, i64 %2 ; <double*> [#uses=1]
%4 = load double* %3, align 8 ; <double> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
%5 = fmul double %4, 3.900000e+00 ; <double> [#uses=1]
Generalize the cast-of-addrec folding to handle folding of SCEVs like (sext i8 {-128,+,1} to i64) to i64 {-128,+,1}, where the iteration crosses from negative to positive, but is still safe if the trip count is within range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70421 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 22:28:28 +00:00
%6 = sext i8 %0 to i64 ; <i64> [#uses=1]
%7 = getelementptr double* %x, i64 %6 ; <double*> [#uses=1]
store double %5, double* %7, align 8
%8 = add i64 %i.0.reg2mem.0, -1 ; <i64> [#uses=2]
%9 = icmp sgt i64 %8, 127 ; <i1> [#uses=1]
br i1 %9, label %return, label %bb1
return: ; preds = %bb1
ret void
}
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