2013-02-05 13:24:56 +00:00
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//===- AArch64.td - Describe the AArch64 Target Machine -------*- tblgen -*-==//
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2013-01-31 12:12:40 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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2013-02-14 16:17:01 +00:00
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//
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2013-01-31 12:12:40 +00:00
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// This is the top level entry point for the AArch64 target.
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2013-02-14 16:17:01 +00:00
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//
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2013-01-31 12:12:40 +00:00
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// AArch64 Subtarget features.
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//
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2013-10-31 09:32:11 +00:00
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
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"Enable ARMv8 FP">;
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2013-01-31 12:12:40 +00:00
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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2013-10-31 09:32:11 +00:00
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"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
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2013-01-31 12:12:40 +00:00
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable cryptographic instructions">;
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//===----------------------------------------------------------------------===//
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// AArch64 Processors
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//
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include "AArch64Schedule.td"
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2014-02-13 09:46:11 +00:00
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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2014-02-14 04:38:09 +00:00
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def : Processor<"generic", GenericItineraries, [FeatureFPARMv8, FeatureNEON]>;
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2013-01-31 12:12:40 +00:00
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2014-03-06 16:04:00 +00:00
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors",
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[FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto]>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors",
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[FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto]>;
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def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
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def : Processor<"cortex-a57", NoItineraries, [ProcA57]>;
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2014-02-13 09:46:11 +00:00
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2013-01-31 12:12:40 +00:00
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "AArch64RegisterInfo.td"
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include "AArch64CallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "AArch64InstrInfo.td"
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2014-03-13 09:00:13 +00:00
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def AArch64InstrInfo : InstrInfo {
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let noNamedPositionallyEncodedOperands = 1;
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}
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2013-01-31 12:12:40 +00:00
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def AArch64 : Target {
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let InstructionSet = AArch64InstrInfo;
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}
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