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70 lines
3.0 KiB
TableGen
70 lines
3.0 KiB
TableGen
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//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips MSA ASE instructions.
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//
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//===----------------------------------------------------------------------===//
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// Instruction encoding.
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class LD_B_ENC : MSA_I5_FMT<0b110, 0b00, 0b000111>;
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class LD_H_ENC : MSA_I5_FMT<0b110, 0b01, 0b000111>;
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class LD_W_ENC : MSA_I5_FMT<0b110, 0b10, 0b000111>;
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class LD_D_ENC : MSA_I5_FMT<0b110, 0b11, 0b000111>;
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class ST_B_ENC : MSA_I5_FMT<0b111, 0b00, 0b000111>;
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class ST_H_ENC : MSA_I5_FMT<0b111, 0b01, 0b000111>;
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class ST_W_ENC : MSA_I5_FMT<0b111, 0b10, 0b000111>;
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class ST_D_ENC : MSA_I5_FMT<0b111, 0b11, 0b000111>;
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// Instruction desc.
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class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
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Operand MemOpnd = mem, ComplexPattern Addr = addr> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins MemOpnd:$addr);
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string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
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list<dag> Pattern = [(set RCWD:$wd, (TyNode (OpNode Addr:$addr)))];
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InstrItinClass Itinerary = itin;
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}
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class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
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Operand MemOpnd = mem, ComplexPattern Addr = addr> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins RCWD:$wd, MemOpnd:$addr);
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string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
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list<dag> Pattern = [(OpNode (TyNode RCWD:$wd), Addr:$addr)];
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InstrItinClass Itinerary = itin;
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}
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// Load/Store
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class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, NoItinerary, MSA128>;
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class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, NoItinerary, MSA128>;
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class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, NoItinerary, MSA128>;
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class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, NoItinerary, MSA128>;
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class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, NoItinerary, MSA128>;
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class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, NoItinerary, MSA128>;
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class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, NoItinerary, MSA128>;
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class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, NoItinerary, MSA128>;
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// Instruction defs.
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def LD_B: LD_B_ENC, LD_B_DESC, Requires<[HasMSA]>;
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def LD_H: LD_H_ENC, LD_H_DESC, Requires<[HasMSA]>;
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def LD_W: LD_W_ENC, LD_W_DESC, Requires<[HasMSA]>;
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def LD_D: LD_D_ENC, LD_D_DESC, Requires<[HasMSA]>;
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def ST_B: ST_B_ENC, ST_B_DESC, Requires<[HasMSA]>;
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def ST_H: ST_H_ENC, ST_H_DESC, Requires<[HasMSA]>;
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def ST_W: ST_W_ENC, ST_W_DESC, Requires<[HasMSA]>;
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def ST_D: ST_D_ENC, ST_D_DESC, Requires<[HasMSA]>;
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// Patterns.
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class MSAPat<dag pattern, dag result, Predicate pred = HasMSA> :
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Pat<pattern, result>, Requires<[pred]>;
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