6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-24 22:32:47 +00:00
Code Issues Projects Releases Wiki Activity
cdc3b74cfb
llvm-6502/test/CodeGen/PowerPC/ctrloops.ll

80 lines
2.4 KiB
LLVM
Raw Normal View History

Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08 15:38:21 +00:00
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-freebsd10.0"
Enable PPC CTR loop formation by default. Thanks to Jakob's help, this now causes no new test suite failures! Over the entire test suite, this gives an average 1% speedup. The largest speedups are: SingleSource/Benchmarks/Misc/pi - 108% SingleSource/Benchmarks/CoyoteBench/lpbench - 54% MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50% SingleSource/Benchmarks/Shootout/ary3 - 32% SingleSource/Benchmarks/Shootout-C++/matrix - 30% The largest slowdowns are: MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30% MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25% MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22% MultiSource/Applications/d/make_dparser - -14% SingleSource/Benchmarks/Shootout-C++/ary - -13% In light of these slowdowns, additional profiling work is obviously needed! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08 19:19:53 +00:00
; RUN: llc < %s -march=ppc64 | FileCheck %s
Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08 15:38:21 +00:00
@a = common global i32 0, align 4
define void @test1(i32 %c) nounwind {
entry:
br label %for.body
for.body: ; preds = %for.body, %entry
%i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%0 = load volatile i32* @a, align 4, !tbaa !0
%add = add nsw i32 %0, %c
store volatile i32 %add, i32* @a, align 4, !tbaa !0
%inc = add nsw i32 %i.01, 1
%exitcond = icmp eq i32 %inc, 2048
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body
ret void
; CHECK: @test1
Improve ext/trunc patterns on PPC64. The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that would leave self-moves in the final assembly. Replacing those patterns with ones based on the SUBREG builtins yields better-looking code. Thanks to Jakob and Owen for their suggestions in this matter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-09 22:10:19 +00:00
; CHECK-NOT: or 3, 3, 3
Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08 15:38:21 +00:00
; CHECK: mtctr
; CHECK-NOT: addi
; CHECK-NOT: cmplwi
; CHECK: bdnz
}
define void @test2(i32 %c, i32 %d) nounwind {
entry:
%cmp1 = icmp sgt i32 %d, 0
br i1 %cmp1, label %for.body, label %for.end
for.body: ; preds = %entry, %for.body
%i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
%0 = load volatile i32* @a, align 4, !tbaa !0
%add = add nsw i32 %0, %c
store volatile i32 %add, i32* @a, align 4, !tbaa !0
%inc = add nsw i32 %i.02, 1
%exitcond = icmp eq i32 %inc, %d
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
ret void
; CHECK: @test2
; CHECK: mtctr
; CHECK-NOT: addi
; CHECK-NOT: cmplwi
; CHECK: bdnz
}
define void @test3(i32 %c, i32 %d) nounwind {
entry:
%cmp1 = icmp sgt i32 %d, 0
br i1 %cmp1, label %for.body, label %for.end
for.body: ; preds = %entry, %for.body
%i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
%mul = mul nsw i32 %i.02, %c
%0 = load volatile i32* @a, align 4, !tbaa !0
%add = add nsw i32 %0, %mul
store volatile i32 %add, i32* @a, align 4, !tbaa !0
%inc = add nsw i32 %i.02, 1
%exitcond = icmp eq i32 %inc, %d
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
ret void
; CHECK: @test3
; CHECK: mtctr
; CHECK-NOT: addi
; CHECK-NOT: cmplwi
; CHECK: bdnz
}
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}
Reference in New Issue Copy Permalink