llvm-6502/test/CodeGen/Thumb/2014-06-10-thumb1-ldst-opt-bug.ll

; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs -o - | FileCheck %s

define void @foo(i32* %A) #0 {
entry:
; CHECK-LABEL: foo:
; CHECK: push {r7, lr}
; CHECK: ldr
; CHECK-NEXT: ldr
; CHECK-NEXT: bl
  %0 = load i32* %A, align 4
  %arrayidx1 = getelementptr inbounds i32* %A, i32 1
  %1 = load i32* %arrayidx1, align 4
  tail call void @bar(i32* %A, i32 %0, i32 %1) #2
  ret void
}

declare void @bar(i32*, i32, i32) #1
ARM: Fix and re-enable load/store optimizer for Thumb1. In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215729 91177308-0d34-0410-b5e6-96231b3b80d8 2014-08-15 17:00:30 +00:00			`; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs -o - \| FileCheck %s`
Fix a bug in the Thumb1 ARM Load/Store optimizer Previously, the basic block was searched for future uses of the base register, and if necessary any writeback to the base register was reset using a SUB instruction (e.g. before calling a function) just before such a use. However, this step happened before the merged LDM/STM instruction was built. So if there was (e.g.) a function call directly after the not-yet-formed LDM/STM, the pass would first insert a SUB instruction to reset the base register, and then (at the same location, incorrectly) insert the LDM/STM itself. This patch fixes PR19972. Patch by Moritz Roth. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210542 91177308-0d34-0410-b5e6-96231b3b80d8 2014-06-10 16:39:21 +00:00
			`define void @foo(i32* %A) #0 {`
			`entry:`
			`; CHECK-LABEL: foo:`
			`; CHECK: push {r7, lr}`
ARM: Fix and re-enable load/store optimizer for Thumb1. In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215729 91177308-0d34-0410-b5e6-96231b3b80d8 2014-08-15 17:00:30 +00:00			`; CHECK: ldr`
			`; CHECK-NEXT: ldr`
Fix a bug in the Thumb1 ARM Load/Store optimizer Previously, the basic block was searched for future uses of the base register, and if necessary any writeback to the base register was reset using a SUB instruction (e.g. before calling a function) just before such a use. However, this step happened before the merged LDM/STM instruction was built. So if there was (e.g.) a function call directly after the not-yet-formed LDM/STM, the pass would first insert a SUB instruction to reset the base register, and then (at the same location, incorrectly) insert the LDM/STM itself. This patch fixes PR19972. Patch by Moritz Roth. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210542 91177308-0d34-0410-b5e6-96231b3b80d8 2014-06-10 16:39:21 +00:00			`; CHECK-NEXT: bl`
			`%0 = load i32* %A, align 4`
			`%arrayidx1 = getelementptr inbounds i32* %A, i32 1`
			`%1 = load i32* %arrayidx1, align 4`
			`tail call void @bar(i32* %A, i32 %0, i32 %1) #2`
			`ret void`
			`}`

			`declare void @bar(i32*, i32, i32) #1`