llvm-6502/test/CodeGen/ARM/neon_shift.ll

; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s

; <rdar://problem/9055897>
define <4 x i16> @t1(<4 x i32> %a) nounwind {
entry:
; CHECK: vqrshrn.s32 d{{[0-9]+}}, q{{[0-9]*}}, #13
  %x = tail call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %a, <4 x i32> <i32 -13, i32 -13, i32 -13, i32 -13>)
  ret <4 x i16> %x
}

declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8 2014-04-03 16:01:44 +00:00			`; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \| FileCheck %s`
Narrow right shifts need to encode their immediates differently from a normal shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8 2011-03-01 01:00:59 +00:00
			`; <rdar://problem/9055897>`
			`define <4 x i16> @t1(<4 x i32> %a) nounwind {`
			`entry:`
			`; CHECK: vqrshrn.s32 d{{[0-9]+}}, q{{[0-9]*}}, #13`
			`%x = tail call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %a, <4 x i32> <i32 -13, i32 -13, i32 -13, i32 -13>)`
			`ret <4 x i16> %x`
			`}`

			`declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone`