2002-10-29 22:37:54 +00:00
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//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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2005-04-21 23:38:14 +00:00
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//
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2003-10-20 19:43:21 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:38:14 +00:00
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//
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2003-10-20 19:43:21 +00:00
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//===----------------------------------------------------------------------===//
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2005-04-21 23:38:14 +00:00
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//
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2002-10-29 22:37:54 +00:00
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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2009-08-22 20:48:53 +00:00
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#include "X86MCAsmInfo.h"
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2002-10-29 22:37:54 +00:00
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#include "X86TargetMachine.h"
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2002-12-24 00:04:01 +00:00
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#include "X86.h"
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2003-04-23 16:24:55 +00:00
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#include "llvm/PassManager.h"
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2002-10-30 00:47:49 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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2003-01-13 00:51:23 +00:00
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#include "llvm/CodeGen/Passes.h"
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2009-07-14 20:18:05 +00:00
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#include "llvm/Support/FormattedStream.h"
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2004-07-11 04:17:10 +00:00
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#include "llvm/Target/TargetOptions.h"
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2009-07-25 06:49:55 +00:00
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#include "llvm/Target/TargetRegistry.h"
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2003-12-20 01:22:19 +00:00
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using namespace llvm;
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2003-11-11 22:41:34 +00:00
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2009-11-06 10:58:06 +00:00
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static const MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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2009-08-12 07:22:17 +00:00
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Triple TheTriple(TT);
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switch (TheTriple.getOS()) {
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case Triple::Darwin:
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2009-08-22 21:03:30 +00:00
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return new X86MCAsmInfoDarwin(TheTriple);
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2009-08-12 07:22:17 +00:00
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case Triple::MinGW32:
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case Triple::MinGW64:
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case Triple::Cygwin:
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2009-08-22 21:03:30 +00:00
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return new X86MCAsmInfoCOFF(TheTriple);
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2009-08-12 07:22:17 +00:00
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case Triple::Win32:
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2009-08-22 20:48:53 +00:00
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return new X86WinMCAsmInfo(TheTriple);
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2009-08-12 07:22:17 +00:00
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default:
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2009-08-22 20:48:53 +00:00
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return new X86ELFMCAsmInfo(TheTriple);
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2009-08-12 07:22:17 +00:00
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}
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}
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2009-07-15 20:24:03 +00:00
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extern "C" void LLVMInitializeX86Target() {
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2009-07-25 06:49:55 +00:00
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// Register the target.
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RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
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RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
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2009-06-16 20:12:29 +00:00
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2009-08-12 07:22:17 +00:00
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// Register the target asm info.
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2009-08-22 20:48:53 +00:00
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RegisterAsmInfoFn A(TheX86_32Target, createMCAsmInfo);
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RegisterAsmInfoFn B(TheX86_64Target, createMCAsmInfo);
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2009-08-27 08:12:55 +00:00
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// Register the code emitter.
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TargetRegistry::RegisterCodeEmitter(TheX86_32Target, createX86MCCodeEmitter);
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TargetRegistry::RegisterCodeEmitter(TheX86_64Target, createX86MCCodeEmitter);
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2006-09-07 23:39:26 +00:00
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}
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2006-09-08 06:48:29 +00:00
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2009-08-12 07:22:17 +00:00
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2009-08-02 23:37:13 +00:00
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X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT,
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2009-07-15 20:24:03 +00:00
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const std::string &FS)
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2009-08-02 23:37:13 +00:00
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: X86TargetMachine(T, TT, FS, false) {
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2006-09-08 06:48:29 +00:00
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}
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2009-08-02 23:37:13 +00:00
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X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT,
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2009-07-15 20:24:03 +00:00
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const std::string &FS)
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2009-08-02 23:37:13 +00:00
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: X86TargetMachine(T, TT, FS, true) {
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2006-09-08 06:48:29 +00:00
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}
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2009-07-09 03:32:31 +00:00
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/// X86TargetMachine ctor - Create an X86 target.
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2002-10-29 22:37:54 +00:00
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///
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2009-08-02 23:37:13 +00:00
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X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
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2009-07-15 20:24:03 +00:00
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const std::string &FS, bool is64Bit)
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2009-08-11 20:42:37 +00:00
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: LLVMTargetMachine(T, TT),
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2009-08-02 23:37:13 +00:00
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Subtarget(TT, FS, is64Bit),
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2007-08-06 21:48:35 +00:00
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DataLayout(Subtarget.getDataLayout()),
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2005-07-12 01:41:54 +00:00
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FrameInfo(TargetFrameInfo::StackGrowsDown,
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2009-08-03 08:12:53 +00:00
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Subtarget.getStackAlignment(),
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(Subtarget.isTargetWin64() ? -40 :
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(Subtarget.is64Bit() ? -8 : -4))),
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2009-06-11 19:16:03 +00:00
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InstrInfo(*this), JITInfo(*this), TLInfo(*this), ELFWriterInfo(*this) {
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2007-12-22 09:40:20 +00:00
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DefRelocModel = getRelocationModel();
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2009-07-09 03:32:31 +00:00
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// If no relocation model was picked, default as appropriate for the target.
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2008-02-20 11:22:39 +00:00
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if (getRelocationModel() == Reloc::Default) {
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2009-07-09 03:32:31 +00:00
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if (!Subtarget.isTargetDarwin())
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2006-12-04 18:07:10 +00:00
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setRelocationModel(Reloc::Static);
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2009-07-09 03:32:31 +00:00
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else if (Subtarget.is64Bit())
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setRelocationModel(Reloc::PIC_);
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else
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setRelocationModel(Reloc::DynamicNoPIC);
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2008-02-20 11:22:39 +00:00
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}
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Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 02:06:02 +00:00
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2009-07-09 03:15:51 +00:00
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assert(getRelocationModel() != Reloc::Default &&
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"Relocation mode not picked");
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2009-07-09 03:32:31 +00:00
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// If no code model is picked, default to small.
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if (getCodeModel() == CodeModel::Default)
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setCodeModel(CodeModel::Small);
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2009-07-09 03:37:30 +00:00
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// ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
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2009-07-09 03:32:31 +00:00
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// is defined as a model for code which may be used in static or dynamic
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2009-07-09 04:24:46 +00:00
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// executables but not necessarily a shared library. On X86-32 we just
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// compile in -static mode, in x86-64 we use PIC.
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if (getRelocationModel() == Reloc::DynamicNoPIC) {
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if (is64Bit)
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setRelocationModel(Reloc::PIC_);
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else if (!Subtarget.isTargetDarwin())
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setRelocationModel(Reloc::Static);
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}
|
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 02:06:02 +00:00
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2009-07-09 03:37:30 +00:00
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// If we are on Darwin, disallow static relocation model in X86-64 mode, since
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// the Mach-O file format doesn't support it.
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if (getRelocationModel() == Reloc::Static &&
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Subtarget.isTargetDarwin() &&
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is64Bit)
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setRelocationModel(Reloc::PIC_);
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2009-07-09 03:32:31 +00:00
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// Determine the PICStyle based on the target selected.
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if (getRelocationModel() == Reloc::Static) {
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// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
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Subtarget.setPICStyle(PICStyles::None);
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} else if (Subtarget.isTargetCygMing()) {
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2009-07-09 03:15:51 +00:00
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Subtarget.setPICStyle(PICStyles::None);
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} else if (Subtarget.isTargetDarwin()) {
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2007-01-18 22:27:12 +00:00
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if (Subtarget.is64Bit())
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2008-11-28 09:29:37 +00:00
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Subtarget.setPICStyle(PICStyles::RIPRel);
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2009-07-10 20:58:47 +00:00
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else if (getRelocationModel() == Reloc::PIC_)
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Subtarget.setPICStyle(PICStyles::StubPIC);
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else {
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assert(getRelocationModel() == Reloc::DynamicNoPIC);
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Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
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}
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2008-02-20 11:22:39 +00:00
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} else if (Subtarget.isTargetELF()) {
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2007-01-18 22:27:12 +00:00
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if (Subtarget.is64Bit())
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2008-11-28 09:29:37 +00:00
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Subtarget.setPICStyle(PICStyles::RIPRel);
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2007-01-12 19:20:47 +00:00
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else
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2008-11-28 09:29:37 +00:00
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Subtarget.setPICStyle(PICStyles::GOT);
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2008-02-20 11:22:39 +00:00
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}
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2009-07-09 03:15:51 +00:00
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2009-07-09 03:32:31 +00:00
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// Finally, if we have "none" as our PIC style, force to static mode.
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if (Subtarget.getPICStyle() == PICStyles::None)
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setRelocationModel(Reloc::Static);
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2006-02-03 18:59:39 +00:00
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}
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2002-10-29 22:37:54 +00:00
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2006-09-04 04:14:57 +00:00
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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2003-08-05 16:34:44 +00:00
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2009-04-29 23:29:43 +00:00
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bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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2005-08-18 23:53:15 +00:00
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// Install an instruction selector.
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2009-04-29 00:15:41 +00:00
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PM.add(createX86ISelDag(*this, OptLevel));
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2008-10-25 17:46:52 +00:00
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// If we're using Fast-ISel, clean up the mess.
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if (EnableFastISel)
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PM.add(createDeadMachineInstructionElimPass());
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2008-11-12 22:55:05 +00:00
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// Install a pass to insert x87 FP_REG_KILL instructions, as needed.
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PM.add(createX87FPRegKillInserterPass());
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2006-09-04 04:14:57 +00:00
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return false;
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2003-06-18 21:43:21 +00:00
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}
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2009-04-29 23:29:43 +00:00
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bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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2008-04-23 18:23:30 +00:00
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// Calculate and set max stack object alignment early, so we can decide
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// whether we will need stack realignment (and thus FP).
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2008-04-23 18:23:05 +00:00
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PM.add(createX86MaxStackAlignmentCalculatorPass());
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return false; // -print-machineinstr shouldn't print after this.
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}
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2009-04-29 23:29:43 +00:00
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bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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2003-01-13 00:51:23 +00:00
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PM.add(createX86FloatingPointStackifierPass());
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2006-09-04 04:14:57 +00:00
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return true; // -print-machineinstr should print after this.
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}
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2003-01-13 00:51:23 +00:00
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2009-04-29 23:29:43 +00:00
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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2009-06-01 19:57:37 +00:00
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MachineCodeEmitter &MCE) {
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2006-09-04 18:48:41 +00:00
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// FIXME: Move this to TargetJITInfo!
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2008-08-12 21:02:08 +00:00
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// On Darwin, do not override 64-bit setting made in X86TargetMachine().
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if (DefRelocModel == Reloc::Default &&
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2009-07-09 03:37:30 +00:00
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(!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) {
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2007-12-22 09:40:20 +00:00
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setRelocationModel(Reloc::Static);
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2009-07-09 03:37:30 +00:00
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Subtarget.setPICStyle(PICStyles::None);
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}
|
2007-01-12 19:20:47 +00:00
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2008-08-11 23:46:25 +00:00
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// 64-bit JIT places everything in the same buffer except external functions.
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2009-11-16 22:41:33 +00:00
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if (Subtarget.is64Bit())
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2008-08-12 21:02:08 +00:00
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setCodeModel(CodeModel::Large);
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2006-12-20 01:03:20 +00:00
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2006-07-25 20:40:54 +00:00
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PM.add(createX86CodeEmitterPass(*this, MCE));
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2007-07-20 21:56:13 +00:00
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2005-07-11 05:17:48 +00:00
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return false;
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}
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2007-02-08 01:39:44 +00:00
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2009-05-30 20:51:52 +00:00
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
|
2009-06-01 19:57:37 +00:00
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JITCodeEmitter &JCE) {
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2009-05-30 20:51:52 +00:00
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// FIXME: Move this to TargetJITInfo!
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// On Darwin, do not override 64-bit setting made in X86TargetMachine().
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if (DefRelocModel == Reloc::Default &&
|
2009-07-09 03:37:30 +00:00
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(!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) {
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2009-05-30 20:51:52 +00:00
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setRelocationModel(Reloc::Static);
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2009-07-09 03:37:30 +00:00
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Subtarget.setPICStyle(PICStyles::None);
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}
|
2009-05-30 20:51:52 +00:00
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// 64-bit JIT places everything in the same buffer except external functions.
|
2009-11-16 22:41:33 +00:00
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if (Subtarget.is64Bit())
|
2009-05-30 20:51:52 +00:00
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setCodeModel(CodeModel::Large);
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PM.add(createX86JITCodeEmitterPass(*this, JCE));
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return false;
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}
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|
2009-07-06 05:09:34 +00:00
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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ObjectCodeEmitter &OCE) {
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PM.add(createX86ObjectCodeEmitterPass(*this, OCE));
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return false;
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}
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2009-04-29 00:15:41 +00:00
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bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
|
2009-04-29 23:29:43 +00:00
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CodeGenOpt::Level OptLevel,
|
2009-04-29 00:15:41 +00:00
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MachineCodeEmitter &MCE) {
|
2007-02-08 01:39:44 +00:00
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PM.add(createX86CodeEmitterPass(*this, MCE));
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|
return false;
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|
}
|
2008-09-26 19:15:30 +00:00
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|
2009-05-30 20:51:52 +00:00
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bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
|
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|
PM.add(createX86JITCodeEmitterPass(*this, JCE));
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|
return false;
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|
|
|
}
|
|
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|
2009-07-06 05:09:34 +00:00
|
|
|
bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
|
|
|
|
CodeGenOpt::Level OptLevel,
|
|
|
|
ObjectCodeEmitter &OCE) {
|
|
|
|
PM.add(createX86ObjectCodeEmitterPass(*this, OCE));
|
|
|
|
return false;
|
|
|
|
}
|