llvm-6502/lib/Target/R600/Processors.td

//===-- Processors.td - R600 Processor definitions ------------------------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
: Processor<Name, itin, Features>;
def : Proc<"",           R600_VLIW5_Itin,
    [FeatureR600ALUInst, FeatureVertexCache]>;
def : Proc<"r600",       R600_VLIW5_Itin,
    [FeatureR600ALUInst , FeatureVertexCache]>;
def : Proc<"rs880",      R600_VLIW5_Itin,
    [FeatureR600ALUInst]>;
def : Proc<"rv670",      R600_VLIW5_Itin,
    [FeatureR600ALUInst, FeatureFP64, FeatureVertexCache]>;
def : Proc<"rv710",      R600_VLIW5_Itin,
    [FeatureVertexCache]>;
def : Proc<"rv730",      R600_VLIW5_Itin,
    [FeatureVertexCache]>;
def : Proc<"rv770",      R600_VLIW5_Itin,
    [FeatureFP64, FeatureVertexCache]>;
def : Proc<"cedar",      R600_VLIW5_Itin,
    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
def : Proc<"redwood",    R600_VLIW5_Itin,
    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
def : Proc<"sumo",       R600_VLIW5_Itin,
    [FeatureByteAddress, FeatureImages]>;
def : Proc<"juniper",    R600_VLIW5_Itin,
    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
def : Proc<"cypress",    R600_VLIW5_Itin,
    [FeatureByteAddress, FeatureImages, FeatureFP64, FeatureVertexCache]>;
def : Proc<"barts",      R600_VLIW5_Itin,
    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
def : Proc<"turks",      R600_VLIW5_Itin,
    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
def : Proc<"caicos",     R600_VLIW5_Itin,
    [FeatureByteAddress, FeatureImages]>;
def : Proc<"cayman",     R600_VLIW4_Itin,
    [FeatureByteAddress, FeatureImages, FeatureFP64]>;def : Proc<"SI",         SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"tahiti",     SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"pitcairn",   SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"verde",      SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"oland",      SI_Itin, [Feature64BitPtr, FeatureFP64]>;
def : Proc<"hainan",     SI_Itin, [Feature64BitPtr, FeatureFP64]>;
R600: Clean up comments in Processors.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181032 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-03 17:21:14 +00:00			`//===-- Processors.td - R600 Processor definitions ------------------------===//`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-11 21:25:42 +00:00			`//`
			`// The LLVM Compiler Infrastructure`
			`//`
			`// This file is distributed under the University of Illinois Open Source`
			`// License. See LICENSE.TXT for details.`
			`//`
			`//===----------------------------------------------------------------------===//`

			`class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>`
			`: Processor<Name, itin, Features>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureR600ALUInst, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"r600", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureR600ALUInst , FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"rs880", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureR600ALUInst]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"rv670", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureR600ALUInst, FeatureFP64, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"rv710", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"rv730", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"rv770", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureFP64, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"cedar", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"redwood", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"sumo", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"juniper", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"cypress", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages, FeatureFP64, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"barts", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"turks", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages, FeatureVertexCache]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"caicos", R600_VLIW5_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages]>;`
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:14:17 +00:00			`def : Proc<"cayman", R600_VLIW4_Itin,`
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-30 00:13:39 +00:00			`[FeatureByteAddress, FeatureImages, FeatureFP64]>;def : Proc<"SI", SI_Itin, [Feature64BitPtr, FeatureFP64]>;`
R600/SI: Add processor types for each SI variant Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178928 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-05 23:31:35 +00:00			`def : Proc<"tahiti", SI_Itin, [Feature64BitPtr, FeatureFP64]>;`
			`def : Proc<"pitcairn", SI_Itin, [Feature64BitPtr, FeatureFP64]>;`
			`def : Proc<"verde", SI_Itin, [Feature64BitPtr, FeatureFP64]>;`
			`def : Proc<"oland", SI_Itin, [Feature64BitPtr, FeatureFP64]>;`
R600/SI: Add processor type for Hainan asic Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181792 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-14 14:42:56 +00:00			`def : Proc<"hainan", SI_Itin, [Feature64BitPtr, FeatureFP64]>;`