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llvm-6502/test/MC/SystemZ/tokens.s

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[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t
# RUN: FileCheck < %t %s
#CHECK: error: invalid instruction
#CHECK: foo 100, 200
[SystemZ] Add the MVC instruction This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 14:56:45 +00:00
#CHECK: error: unknown token in expression
[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
#CHECK: foo 100(, 200
[SystemZ] Add the MVC instruction This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 14:56:45 +00:00
#CHECK: error: invalid instruction
#CHECK: foo 100(200), 300
[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
#CHECK: error: register expected
[SystemZ] Add the MVC instruction This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 14:56:45 +00:00
#CHECK: foo 100(200,), 300
#CHECK: error: %r0 used in an address
#CHECK: foo 100(200,%r0), 300
#CHECK: error: invalid instruction
#CHECK: foo 100(200,%r1), 300
[SystemZ] Add z13 vector facility and MC support This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:23:40 +00:00
#CHECK: error: invalid address register
[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
#CHECK: foo 100(%a0), 200
#CHECK: error: %r0 used in an address
#CHECK: foo 100(%r0), 200
[SystemZ] Add z13 vector facility and MC support This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:23:40 +00:00
#CHECK: error: %r0 used in an address
#CHECK: foo 100(%v1,%r0), 200
#CHECK: error: invalid instruction
#CHECK: foo 100(%v0,%r1), 200
#CHECK: error: invalid instruction
#CHECK: foo 100(%v31), 200
[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
#CHECK: error: invalid operand
#CHECK: foo 100(%r1,%a0), 200
#CHECK: error: %r0 used in an address
#CHECK: foo 100(%r1,%r0), 200
#CHECK: error: unexpected token in address
#CHECK: foo 100(%r1,%r2, 200
#CHECK: error: invalid instruction
#CHECK: foo 100(%r1,%r2), 200
#CHECK: error: unexpected token in argument list
#CHECK: foo 100(%r1,%r2)(, 200
#CHECK: error: invalid instruction
#CHECK: foo %r0, 200
#CHECK: error: invalid instruction
#CHECK: foo %r15, 200
#CHECK: error: invalid register
#CHECK: foo %r16, 200
#CHECK: error: invalid instruction
#CHECK: foo %f0, 200
#CHECK: error: invalid instruction
#CHECK: foo %f15, 200
#CHECK: error: invalid register
#CHECK: foo %f16, 200
#CHECK: error: invalid instruction
#CHECK: foo %a0, 200
#CHECK: error: invalid instruction
#CHECK: foo %a15, 200
#CHECK: error: invalid register
#CHECK: foo %a16, 200
[SystemZ] Add z13 vector facility and MC support This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:23:40 +00:00
#CHECK: error: invalid instruction
#CHECK: foo %v0, 200
#CHECK: error: invalid instruction
#CHECK: foo %v31, 200
#CHECK: error: invalid register
#CHECK: foo %v32, 200
[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
#CHECK: error: invalid register
#CHECK: foo %c, 200
#CHECK: error: invalid register
#CHECK: foo %, 200
#CHECK: error: unknown token in expression
#CHECK: foo {, 200
foo 100, 200
foo 100(, 200
[SystemZ] Add the MVC instruction This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 14:56:45 +00:00
foo 100(200), 300
foo 100(200,), 300
foo 100(200,%r0), 300
foo 100(200,%r1), 300
[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
foo 100(%a0), 200
foo 100(%r0), 200
[SystemZ] Add z13 vector facility and MC support This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:23:40 +00:00
foo 100(%v1,%r0), 200
foo 100(%v0,%r1), 200
foo 100(%v31), 200
[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
foo 100(%r1,%a0), 200
foo 100(%r1,%r0), 200
foo 100(%r1,%r2, 200
foo 100(%r1,%r2), 200
foo 100(%r1,%r2)(, 200
foo %r0, 200
foo %r15, 200
foo %r16, 200
foo %f0, 200
foo %f15, 200
foo %f16, 200
foo %a0, 200
foo %a15, 200
foo %a16, 200
[SystemZ] Add z13 vector facility and MC support This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:23:40 +00:00
foo %v0, 200
foo %v31, 200
foo %v32, 200
[SystemZ] Improve AsmParser handling of invalid instructions Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 14:26:46 +00:00
foo %c, 200
foo %, 200
foo {, 200
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