llvm-6502/test/CodeGen/R600/selectcc-cnd.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s

;CHECK-NOT: SETE
;CHECK: CNDE {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x,
;CHECK: 1073741824
define void @test(float addrspace(1)* %out, float addrspace(1)* %in) {
  %1 = load float, float addrspace(1)* %in
  %2 = fcmp oeq float %1, 0.0
  %3 = select i1 %2, float 1.0, float 2.0
  store float %3, float addrspace(1)* %out
  ret void
}
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-11 21:25:42 +00:00			`;RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s`

			`;CHECK-NOT: SETE`
R600: Non vector only instruction can be scheduled on trans unit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8 2013-09-04 19:53:46 +00:00			`;CHECK: CNDE {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x,`
			`;CHECK: 1073741824`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-11 21:25:42 +00:00			`define void @test(float addrspace(1)* %out, float addrspace(1)* %in) {`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8 2015-02-27 21:17:42 +00:00			`%1 = load float, float addrspace(1)* %in`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-11 21:25:42 +00:00			`%2 = fcmp oeq float %1, 0.0`
			`%3 = select i1 %2, float 1.0, float 2.0`
			`store float %3, float addrspace(1)* %out`
			`ret void`
			`}`