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llvm-6502/test/CodeGen/ARM/dwarf-unwind.ll

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ARM/Dwarf: correctly align stack before callee-saved VPRs We were making an attempt to do this by adding an extra callee-saved GPR (so that there was an even number in the list), but when that failed we went ahead and pushed anyway. This had a couple of potential issues: + The .cfi directives we emit misplaced dN because they were based on PrologEpilogInserter's calculation. + Unaligned stores can be less efficient. + Unaligned stores can actually fault (likely only an issue in niche cases, but possible). This adds a final explicit stack adjustment if all other options fail, so that the actual locations of the registers match up with where they should be. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221320 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 00:27:13 +00:00
; RUN: llc -mtriple=thumbv7-netbsd-eabi -o - %s | FileCheck %s
declare void @bar()
; ARM's frame lowering attempts to tack another callee-saved register onto the
; list when it detects a potential misaligned VFP store. However, if there are
; none available it used to just vpush anyway and misreport the location of the
; registers in unwind info. Since there are benefits to aligned stores, it's
; better to correct the code than the .cfi_offset directive.
define void @test_dpr_align(i8 %l, i8 %r) {
; CHECK-LABEL: test_dpr_align:
; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
ARM: refactor .cfi_def_cfa_offset emission. We use to track quite a few "adjusted" offsets through the FrameLowering code to account for changes in the prologue instructions as we went and allow the emission of correct CFA annotations. However, we were missing a couple of cases and the code was almost impenetrable. It's easier to just add any stack-adjusting instruction to a list and emit them together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222057 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 22:45:33 +00:00
; CHECK: .cfi_def_cfa_offset 36
ARM/Dwarf: correctly align stack before callee-saved VPRs We were making an attempt to do this by adding an extra callee-saved GPR (so that there was an even number in the list), but when that failed we went ahead and pushed anyway. This had a couple of potential issues: + The .cfi directives we emit misplaced dN because they were based on PrologEpilogInserter's calculation. + Unaligned stores can be less efficient. + Unaligned stores can actually fault (likely only an issue in niche cases, but possible). This adds a final explicit stack adjustment if all other options fail, so that the actual locations of the registers match up with where they should be. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221320 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 00:27:13 +00:00
; CHECK: sub sp, #4
ARM: refactor .cfi_def_cfa_offset emission. We use to track quite a few "adjusted" offsets through the FrameLowering code to account for changes in the prologue instructions as we went and allow the emission of correct CFA annotations. However, we were missing a couple of cases and the code was almost impenetrable. It's easier to just add any stack-adjusting instruction to a list and emit them together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222057 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 22:45:33 +00:00
; CHECK: .cfi_def_cfa_offset 40
ARM/Dwarf: correctly align stack before callee-saved VPRs We were making an attempt to do this by adding an extra callee-saved GPR (so that there was an even number in the list), but when that failed we went ahead and pushed anyway. This had a couple of potential issues: + The .cfi directives we emit misplaced dN because they were based on PrologEpilogInserter's calculation. + Unaligned stores can be less efficient. + Unaligned stores can actually fault (likely only an issue in niche cases, but possible). This adds a final explicit stack adjustment if all other options fail, so that the actual locations of the registers match up with where they should be. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221320 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 00:27:13 +00:00
; CHECK: vpush {d8}
; CHECK: .cfi_offset d8, -48
; CHECK-NOT: sub sp
; [...]
; CHECK: bl bar
; CHECK-NOT: add sp
; CHECK: vpop {d8}
; CHECK: add sp, #4
; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
call void @bar()
ret void
}
; The prologue (but not the epilogue) can be made more space efficient by
; chucking an argument register into the list. Not worth it in general though,
; "sub sp, #4" is likely faster.
define void @test_dpr_align_tiny(i8 %l, i8 %r) minsize {
; CHECK-LABEL: test_dpr_align_tiny:
; CHECK: push.w {r3, r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NOT: sub sp
; CHECK: vpush {d8}
; CHECK: .cfi_offset d8, -48
; CHECK-NOT: sub sp
; [...]
; CHECK: bl bar
; CHECK-NOT: add sp
; CHECK: vpop {d8}
; CHECK: add sp, #4
; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
call void @bar()
ret void
}
; However, we shouldn't do a 2-step align/adjust if there are no DPRs to be
; saved.
define void @test_nodpr_noalign(i8 %l, i8 %r) {
; CHECK-LABEL: test_nodpr_noalign:
; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NOT: sub sp
; CHECK: sub sp, #12
; CHECK-NOT: sub sp
; [...]
; CHECK: bl bar
; CHECK-NOT: add sp
; CHECK: add sp, #12
; CHECK-NOT: add sp
; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
alloca i64
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"()
call void @bar()
ret void
}
ARM: correctly calculate the offset of FP in its push. When we folded the DPR alignment gap into a push, we weren't noting the extra distance from the beginning of the push to the FP, and so FP ended up pointing at an incorrect offset. The .cfi_def_cfa_offset directives are still wrong in this case, but I think that can be improved by refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222056 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 22:45:31 +00:00
define void @test_frame_pointer_offset() minsize "no-frame-pointer-elim"="true" {
; CHECK-LABEL: test_frame_pointer_offset:
; CHECK: push.w {r3, r4, r5, r6, r7, r8, r9, r10, r11, lr}
ARM: refactor .cfi_def_cfa_offset emission. We use to track quite a few "adjusted" offsets through the FrameLowering code to account for changes in the prologue instructions as we went and allow the emission of correct CFA annotations. However, we were missing a couple of cases and the code was almost impenetrable. It's easier to just add any stack-adjusting instruction to a list and emit them together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222057 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 22:45:33 +00:00
; CHECK: .cfi_def_cfa_offset 40
ARM: correctly calculate the offset of FP in its push. When we folded the DPR alignment gap into a push, we weren't noting the extra distance from the beginning of the push to the FP, and so FP ended up pointing at an incorrect offset. The .cfi_def_cfa_offset directives are still wrong in this case, but I think that can be improved by refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222056 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 22:45:31 +00:00
; CHECK: add r7, sp, #16
ARM: refactor .cfi_def_cfa_offset emission. We use to track quite a few "adjusted" offsets through the FrameLowering code to account for changes in the prologue instructions as we went and allow the emission of correct CFA annotations. However, we were missing a couple of cases and the code was almost impenetrable. It's easier to just add any stack-adjusting instruction to a list and emit them together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222057 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 22:45:33 +00:00
; CHECK: .cfi_def_cfa r7, 24
; CHECK-NOT: .cfi_def_cfa_offset
ARM: correctly calculate the offset of FP in its push. When we folded the DPR alignment gap into a push, we weren't noting the extra distance from the beginning of the push to the FP, and so FP ended up pointing at an incorrect offset. The .cfi_def_cfa_offset directives are still wrong in this case, but I think that can be improved by refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222056 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 22:45:31 +00:00
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
call void @bar()
ret void
}
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