2004-08-01 05:59:33 +00:00
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//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
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2005-04-22 00:00:37 +00:00
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//
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2004-08-01 05:59:33 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:37:13 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 00:00:37 +00:00
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//
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2004-08-01 05:59:33 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is emits an assembly printer for the current target.
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// Note that this is currently fairly skeletal, but will grow over time.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmWriterEmitter.h"
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2010-02-09 21:50:41 +00:00
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#include "AsmWriterInst.h"
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2004-08-01 05:59:33 +00:00
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#include "CodeGenTarget.h"
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2004-08-14 22:50:53 +00:00
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#include "Record.h"
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2009-09-14 01:19:16 +00:00
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#include "StringToOffsetTable.h"
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2006-07-18 17:18:03 +00:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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2005-01-22 18:50:10 +00:00
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#include <algorithm>
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2004-08-01 05:59:33 +00:00
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using namespace llvm;
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This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
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static void PrintCases(std::vector<std::pair<std::string,
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2009-07-03 00:10:29 +00:00
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AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
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This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
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O << " case " << OpsToPrint.back().first << ": ";
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AsmWriterOperand TheOp = OpsToPrint.back().second;
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OpsToPrint.pop_back();
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// Check to see if any other operands are identical in this list, and if so,
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// emit a case label for them.
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for (unsigned i = OpsToPrint.size(); i != 0; --i)
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if (OpsToPrint[i-1].second == TheOp) {
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O << "\n case " << OpsToPrint[i-1].first << ": ";
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OpsToPrint.erase(OpsToPrint.begin()+i-1);
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}
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// Finally, emit the code.
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2006-07-18 17:18:03 +00:00
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O << TheOp.getCode();
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This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
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O << "break;\n";
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}
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Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
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/// EmitInstructions - Emit the last instruction in the vector and any other
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/// instructions that are suitably similar to it.
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static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
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2009-07-03 00:10:29 +00:00
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raw_ostream &O) {
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Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
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AsmWriterInst FirstInst = Insts.back();
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Insts.pop_back();
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std::vector<AsmWriterInst> SimilarInsts;
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unsigned DifferingOperand = ~0;
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for (unsigned i = Insts.size(); i != 0; --i) {
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2005-01-22 19:22:23 +00:00
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unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
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if (DiffOp != ~1U) {
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Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
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if (DifferingOperand == ~0U) // First match!
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DifferingOperand = DiffOp;
|
|
|
|
|
|
|
|
// If this differs in the same operand as the rest of the instructions in
|
|
|
|
// this class, move it to the SimilarInsts list.
|
2005-01-22 19:22:23 +00:00
|
|
|
if (DifferingOperand == DiffOp || DiffOp == ~0U) {
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
SimilarInsts.push_back(Insts[i-1]);
|
|
|
|
Insts.erase(Insts.begin()+i-1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-01 17:01:17 +00:00
|
|
|
O << " case " << FirstInst.CGI->Namespace << "::"
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
<< FirstInst.CGI->TheDef->getName() << ":\n";
|
|
|
|
for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
|
2006-05-01 17:01:17 +00:00
|
|
|
O << " case " << SimilarInsts[i].CGI->Namespace << "::"
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
<< SimilarInsts[i].CGI->TheDef->getName() << ":\n";
|
|
|
|
for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
|
|
|
|
if (i != DifferingOperand) {
|
|
|
|
// If the operand is the same for all instructions, just print it.
|
2006-07-18 17:18:03 +00:00
|
|
|
O << " " << FirstInst.Operands[i].getCode();
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
} else {
|
|
|
|
// If this is the operand that varies between all of the instructions,
|
|
|
|
// emit a switch for just this operand now.
|
|
|
|
O << " switch (MI->getOpcode()) {\n";
|
This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
|
|
|
std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
|
2006-05-01 17:01:17 +00:00
|
|
|
OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
|
This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
|
|
|
FirstInst.CGI->TheDef->getName(),
|
|
|
|
FirstInst.Operands[i]));
|
2005-04-22 00:00:37 +00:00
|
|
|
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
|
This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
|
|
|
AsmWriterInst &AWI = SimilarInsts[si];
|
2006-05-01 17:01:17 +00:00
|
|
|
OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
|
This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
|
|
|
AWI.CGI->TheDef->getName(),
|
|
|
|
AWI.Operands[i]));
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
}
|
This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all. On the X86,
this turns this code:
switch (MI->getOpcode()) {
case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
}
into this:
switch (MI->getOpcode()) {
case X86::ADC32mi:
case X86::ADC32mr:
case X86::ADD32mi:
case X86::ADD32mr:
case X86::AND32mi:
case X86::AND32mr:
case X86::CMP32mi:
case X86::CMP32mr:
case X86::MOV32mi:
case X86::MOV32mr:
case X86::OR32mi:
case X86::OR32mr:
case X86::SBB32mi:
case X86::SBB32mr:
case X86::SHLD32mrCL:
case X86::SHRD32mrCL:
case X86::SUB32mi:
case X86::SUB32mr:
case X86::TEST32mi:
case X86::TEST32mr:
case X86::XCHG32mr:
case X86::XOR32mi:
case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
case X86::ADC32mi8:
case X86::ADD32mi8:
case X86::AND32mi8:
case X86::OR32mi8:
case X86::ROL32mi:
case X86::ROR32mi:
case X86::SAR32mi:
case X86::SBB32mi8:
case X86::SHL32mi:
case X86::SHR32mi:
case X86::SUB32mi8:
case X86::TEST8mi:
case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
}
After this, the generated asmwriters look pretty much as though they were
generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19760 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 20:31:17 +00:00
|
|
|
std::reverse(OpsToPrint.begin(), OpsToPrint.end());
|
|
|
|
while (!OpsToPrint.empty())
|
|
|
|
PrintCases(OpsToPrint, O);
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
O << " }";
|
|
|
|
}
|
|
|
|
O << "\n";
|
|
|
|
}
|
|
|
|
O << " break;\n";
|
|
|
|
}
|
2005-01-22 17:32:42 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
void AsmWriterEmitter::
|
2010-09-29 22:32:50 +00:00
|
|
|
FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
|
2006-07-18 18:28:27 +00:00
|
|
|
std::vector<unsigned> &InstIdxs,
|
|
|
|
std::vector<unsigned> &InstOpsUsed) const {
|
2006-07-18 19:27:30 +00:00
|
|
|
InstIdxs.assign(NumberedInstructions.size(), ~0U);
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// This vector parallels UniqueOperandCommands, keeping track of which
|
|
|
|
// instructions each case are used for. It is a comma separated string of
|
|
|
|
// enums.
|
|
|
|
std::vector<std::string> InstrsForCase;
|
|
|
|
InstrsForCase.resize(UniqueOperandCommands.size());
|
2006-07-18 18:28:27 +00:00
|
|
|
InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
|
|
const AsmWriterInst *Inst = getAsmWriterInstByID(i);
|
2010-07-16 23:10:00 +00:00
|
|
|
if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc.
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
std::string Command;
|
2006-07-18 17:56:07 +00:00
|
|
|
if (Inst->Operands.empty())
|
2006-07-18 17:18:03 +00:00
|
|
|
continue; // Instruction already done.
|
2006-07-18 17:50:22 +00:00
|
|
|
|
2006-07-18 17:56:07 +00:00
|
|
|
Command = " " + Inst->Operands[0].getCode() + "\n";
|
2006-07-18 17:50:22 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Check to see if we already have 'Command' in UniqueOperandCommands.
|
|
|
|
// If not, add it.
|
|
|
|
bool FoundIt = false;
|
|
|
|
for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
|
|
|
|
if (UniqueOperandCommands[idx] == Command) {
|
|
|
|
InstIdxs[i] = idx;
|
|
|
|
InstrsForCase[idx] += ", ";
|
|
|
|
InstrsForCase[idx] += Inst->CGI->TheDef->getName();
|
|
|
|
FoundIt = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (!FoundIt) {
|
|
|
|
InstIdxs[i] = UniqueOperandCommands.size();
|
|
|
|
UniqueOperandCommands.push_back(Command);
|
|
|
|
InstrsForCase.push_back(Inst->CGI->TheDef->getName());
|
2006-07-18 18:28:27 +00:00
|
|
|
|
|
|
|
// This command matches one operand so far.
|
|
|
|
InstOpsUsed.push_back(1);
|
|
|
|
}
|
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 18:28:27 +00:00
|
|
|
// For each entry of UniqueOperandCommands, there is a set of instructions
|
|
|
|
// that uses it. If the next command of all instructions in the set are
|
|
|
|
// identical, fold it into the command.
|
|
|
|
for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
|
|
|
|
CommandIdx != e; ++CommandIdx) {
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 18:28:27 +00:00
|
|
|
for (unsigned Op = 1; ; ++Op) {
|
|
|
|
// Scan for the first instruction in the set.
|
|
|
|
std::vector<unsigned>::iterator NIT =
|
|
|
|
std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
|
|
|
|
if (NIT == InstIdxs.end()) break; // No commonality.
|
|
|
|
|
|
|
|
// If this instruction has no more operands, we isn't anything to merge
|
|
|
|
// into this command.
|
2010-09-29 22:32:50 +00:00
|
|
|
const AsmWriterInst *FirstInst =
|
2006-07-18 18:28:27 +00:00
|
|
|
getAsmWriterInstByID(NIT-InstIdxs.begin());
|
|
|
|
if (!FirstInst || FirstInst->Operands.size() == Op)
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Otherwise, scan to see if all of the other instructions in this command
|
|
|
|
// set share the operand.
|
|
|
|
bool AllSame = true;
|
2009-07-29 20:10:24 +00:00
|
|
|
// Keep track of the maximum, number of operands or any
|
|
|
|
// instruction we see in the group.
|
|
|
|
size_t MaxSize = FirstInst->Operands.size();
|
|
|
|
|
2006-07-18 18:28:27 +00:00
|
|
|
for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
|
|
|
|
NIT != InstIdxs.end();
|
|
|
|
NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
|
|
|
|
// Okay, found another instruction in this command set. If the operand
|
|
|
|
// matches, we're ok, otherwise bail out.
|
2010-09-29 22:32:50 +00:00
|
|
|
const AsmWriterInst *OtherInst =
|
2006-07-18 18:28:27 +00:00
|
|
|
getAsmWriterInstByID(NIT-InstIdxs.begin());
|
2009-07-29 20:10:24 +00:00
|
|
|
|
|
|
|
if (OtherInst &&
|
|
|
|
OtherInst->Operands.size() > FirstInst->Operands.size())
|
|
|
|
MaxSize = std::max(MaxSize, OtherInst->Operands.size());
|
|
|
|
|
2006-07-18 18:28:27 +00:00
|
|
|
if (!OtherInst || OtherInst->Operands.size() == Op ||
|
|
|
|
OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
|
|
|
|
AllSame = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!AllSame) break;
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 18:28:27 +00:00
|
|
|
// Okay, everything in this command set has the same next operand. Add it
|
|
|
|
// to UniqueOperandCommands and remember that it was consumed.
|
|
|
|
std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 18:28:27 +00:00
|
|
|
UniqueOperandCommands[CommandIdx] += Command;
|
|
|
|
InstOpsUsed[CommandIdx]++;
|
2006-07-18 17:18:03 +00:00
|
|
|
}
|
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Prepend some of the instructions each case is used for onto the case val.
|
|
|
|
for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
|
|
|
|
std::string Instrs = InstrsForCase[i];
|
|
|
|
if (Instrs.size() > 70) {
|
|
|
|
Instrs.erase(Instrs.begin()+70, Instrs.end());
|
|
|
|
Instrs += "...";
|
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
if (!Instrs.empty())
|
2010-09-29 22:32:50 +00:00
|
|
|
UniqueOperandCommands[i] = " // " + Instrs + "\n" +
|
2006-07-18 17:18:03 +00:00
|
|
|
UniqueOperandCommands[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-10-17 20:43:42 +00:00
|
|
|
static void UnescapeString(std::string &Str) {
|
|
|
|
for (unsigned i = 0; i != Str.size(); ++i) {
|
|
|
|
if (Str[i] == '\\' && i != Str.size()-1) {
|
|
|
|
switch (Str[i+1]) {
|
|
|
|
default: continue; // Don't execute the code after the switch.
|
|
|
|
case 'a': Str[i] = '\a'; break;
|
|
|
|
case 'b': Str[i] = '\b'; break;
|
|
|
|
case 'e': Str[i] = 27; break;
|
|
|
|
case 'f': Str[i] = '\f'; break;
|
|
|
|
case 'n': Str[i] = '\n'; break;
|
|
|
|
case 'r': Str[i] = '\r'; break;
|
|
|
|
case 't': Str[i] = '\t'; break;
|
|
|
|
case 'v': Str[i] = '\v'; break;
|
|
|
|
case '"': Str[i] = '\"'; break;
|
|
|
|
case '\'': Str[i] = '\''; break;
|
|
|
|
case '\\': Str[i] = '\\'; break;
|
|
|
|
}
|
|
|
|
// Nuke the second character.
|
|
|
|
Str.erase(Str.begin()+i+1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-09-13 20:08:00 +00:00
|
|
|
/// EmitPrintInstruction - Generate the code for the "printInstruction" method
|
|
|
|
/// implementation.
|
|
|
|
void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
|
2010-12-13 00:23:57 +00:00
|
|
|
CodeGenTarget Target(Records);
|
2004-08-14 22:50:53 +00:00
|
|
|
Record *AsmWriter = Target.getAsmWriter();
|
2004-10-03 20:19:02 +00:00
|
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
2010-09-30 01:29:54 +00:00
|
|
|
bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter");
|
|
|
|
const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2004-08-01 05:59:33 +00:00
|
|
|
O <<
|
|
|
|
"/// printInstruction - This method is automatically generated by tablegen\n"
|
2009-09-13 20:08:00 +00:00
|
|
|
"/// from the instruction set description.\n"
|
2009-08-08 01:32:19 +00:00
|
|
|
"void " << Target.getName() << ClassName
|
2010-09-30 01:29:54 +00:00
|
|
|
<< "::printInstruction(const " << MachineInstrClassName
|
|
|
|
<< " *MI, raw_ostream &O) {\n";
|
2004-08-01 05:59:33 +00:00
|
|
|
|
2005-01-22 17:40:38 +00:00
|
|
|
std::vector<AsmWriterInst> Instructions;
|
|
|
|
|
2004-08-01 05:59:33 +00:00
|
|
|
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
|
|
|
|
E = Target.inst_end(); I != E; ++I)
|
2010-03-19 01:00:55 +00:00
|
|
|
if (!(*I)->AsmString.empty() &&
|
|
|
|
(*I)->TheDef->getName() != "PHI")
|
2010-02-09 23:06:35 +00:00
|
|
|
Instructions.push_back(
|
2010-09-29 22:32:50 +00:00
|
|
|
AsmWriterInst(**I,
|
2010-02-09 23:06:35 +00:00
|
|
|
AsmWriter->getValueAsInt("Variant"),
|
|
|
|
AsmWriter->getValueAsInt("FirstOperandColumn"),
|
|
|
|
AsmWriter->getValueAsInt("OperandSpacing")));
|
2005-01-22 17:40:38 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Get the instruction numbering.
|
2010-03-19 00:34:35 +00:00
|
|
|
NumberedInstructions = Target.getInstructionsByEnumValue();
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-14 22:59:11 +00:00
|
|
|
// Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
|
|
|
|
// all machine instructions are necessarily being printed, so there may be
|
|
|
|
// target instructions not in this map.
|
|
|
|
for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
|
|
|
|
CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
|
|
|
|
|
|
|
|
// Build an aggregate string, and build a table of offsets into it.
|
2009-09-14 01:16:36 +00:00
|
|
|
StringToOffsetTable StringTable;
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-09-27 16:44:09 +00:00
|
|
|
/// OpcodeInfo - This encodes the index of the string to use for the first
|
2006-07-18 17:32:27 +00:00
|
|
|
/// chunk of the output as well as indices used for operand printing.
|
|
|
|
std::vector<unsigned> OpcodeInfo;
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:32:27 +00:00
|
|
|
unsigned MaxStringIdx = 0;
|
2006-07-14 22:59:11 +00:00
|
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
|
|
AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
|
|
|
|
unsigned Idx;
|
2006-07-19 01:39:06 +00:00
|
|
|
if (AWI == 0) {
|
2006-07-14 22:59:11 +00:00
|
|
|
// Something not handled by the asmwriter printer.
|
2009-09-14 01:16:36 +00:00
|
|
|
Idx = ~0U;
|
2010-09-29 22:32:50 +00:00
|
|
|
} else if (AWI->Operands[0].OperandType !=
|
2006-07-19 01:39:06 +00:00
|
|
|
AsmWriterOperand::isLiteralTextOperand ||
|
|
|
|
AWI->Operands[0].Str.empty()) {
|
|
|
|
// Something handled by the asmwriter printer, but with no leading string.
|
2009-09-14 01:16:36 +00:00
|
|
|
Idx = StringTable.GetOrAddStringOffset("");
|
2006-07-14 22:59:11 +00:00
|
|
|
} else {
|
2009-09-14 01:16:36 +00:00
|
|
|
std::string Str = AWI->Operands[0].Str;
|
|
|
|
UnescapeString(Str);
|
|
|
|
Idx = StringTable.GetOrAddStringOffset(Str);
|
|
|
|
MaxStringIdx = std::max(MaxStringIdx, Idx);
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-14 22:59:11 +00:00
|
|
|
// Nuke the string from the operand list. It is now handled!
|
|
|
|
AWI->Operands.erase(AWI->Operands.begin());
|
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2009-09-14 01:16:36 +00:00
|
|
|
// Bias offset by one since we want 0 as a sentinel.
|
|
|
|
OpcodeInfo.push_back(Idx+1);
|
2006-07-18 17:18:03 +00:00
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:32:27 +00:00
|
|
|
// Figure out how many bits we used for the string index.
|
2009-09-14 01:16:36 +00:00
|
|
|
unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// To reduce code size, we compactify common instructions into a few bits
|
|
|
|
// in the opcode-indexed table.
|
2006-07-18 17:38:46 +00:00
|
|
|
unsigned BitsLeft = 32-AsmStrBits;
|
2006-07-18 17:18:03 +00:00
|
|
|
|
|
|
|
std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:56:07 +00:00
|
|
|
while (1) {
|
2006-07-18 17:18:03 +00:00
|
|
|
std::vector<std::string> UniqueOperandCommands;
|
|
|
|
std::vector<unsigned> InstIdxs;
|
2006-07-18 18:28:27 +00:00
|
|
|
std::vector<unsigned> NumInstOpsHandled;
|
|
|
|
FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
|
|
|
|
NumInstOpsHandled);
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// If we ran out of operands to print, we're done.
|
|
|
|
if (UniqueOperandCommands.empty()) break;
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Compute the number of bits we need to represent these cases, this is
|
|
|
|
// ceil(log2(numentries)).
|
|
|
|
unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// If we don't have enough bits for this operand, don't include it.
|
|
|
|
if (NumBits > BitsLeft) {
|
2009-08-23 04:44:11 +00:00
|
|
|
DEBUG(errs() << "Not enough bits to densely encode " << NumBits
|
|
|
|
<< " more bits\n");
|
2006-07-18 17:18:03 +00:00
|
|
|
break;
|
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Otherwise, we can include this in the initial lookup table. Add it in.
|
|
|
|
BitsLeft -= NumBits;
|
|
|
|
for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
|
2006-07-18 19:27:30 +00:00
|
|
|
if (InstIdxs[i] != ~0U)
|
|
|
|
OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:56:07 +00:00
|
|
|
// Remove the info about this operand.
|
|
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
|
|
if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
|
2006-07-18 18:28:27 +00:00
|
|
|
if (!Inst->Operands.empty()) {
|
|
|
|
unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
|
2006-07-18 19:06:01 +00:00
|
|
|
assert(NumOps <= Inst->Operands.size() &&
|
|
|
|
"Can't remove this many ops!");
|
2006-07-18 18:28:27 +00:00
|
|
|
Inst->Operands.erase(Inst->Operands.begin(),
|
|
|
|
Inst->Operands.begin()+NumOps);
|
|
|
|
}
|
2006-07-18 17:56:07 +00:00
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:56:07 +00:00
|
|
|
// Remember the handlers for this set of operands.
|
2006-07-18 17:18:03 +00:00
|
|
|
TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
|
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
2006-07-18 17:32:27 +00:00
|
|
|
O<<" static const unsigned OpInfo[] = {\n";
|
2006-07-18 17:18:03 +00:00
|
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
2006-07-18 17:38:46 +00:00
|
|
|
O << " " << OpcodeInfo[i] << "U,\t// "
|
2006-07-18 17:32:27 +00:00
|
|
|
<< NumberedInstructions[i]->TheDef->getName() << "\n";
|
2006-07-14 22:59:11 +00:00
|
|
|
}
|
2006-07-18 17:18:03 +00:00
|
|
|
// Add a dummy entry so the array init doesn't end with a comma.
|
2006-07-18 17:32:27 +00:00
|
|
|
O << " 0U\n";
|
2006-07-14 22:59:11 +00:00
|
|
|
O << " };\n\n";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-14 22:59:11 +00:00
|
|
|
// Emit the string itself.
|
2009-09-14 01:16:36 +00:00
|
|
|
O << " const char *AsmStrs = \n";
|
|
|
|
StringTable.EmitString(O);
|
|
|
|
O << ";\n\n";
|
2006-07-14 22:59:11 +00:00
|
|
|
|
2008-02-02 08:39:46 +00:00
|
|
|
O << " O << \"\\t\";\n\n";
|
|
|
|
|
2006-07-14 22:59:11 +00:00
|
|
|
O << " // Emit the opcode for the instruction.\n"
|
2006-07-18 17:32:27 +00:00
|
|
|
<< " unsigned Bits = OpInfo[MI->getOpcode()];\n"
|
2009-08-08 01:32:19 +00:00
|
|
|
<< " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
|
2009-09-14 01:16:36 +00:00
|
|
|
<< " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
|
2009-08-05 21:00:52 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Output the table driven operand information.
|
2006-07-18 17:38:46 +00:00
|
|
|
BitsLeft = 32-AsmStrBits;
|
2006-07-18 17:18:03 +00:00
|
|
|
for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
|
|
|
|
std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
|
2005-01-22 19:22:23 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Compute the number of bits we need to represent these cases, this is
|
|
|
|
// ceil(log2(numentries)).
|
|
|
|
unsigned NumBits = Log2_32_Ceil(Commands.size());
|
|
|
|
assert(NumBits <= BitsLeft && "consistency error");
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Emit code to extract this field from Bits.
|
|
|
|
BitsLeft -= NumBits;
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
O << "\n // Fragment " << i << " encoded into " << NumBits
|
2006-07-18 17:43:54 +00:00
|
|
|
<< " bits for " << Commands.size() << " unique commands.\n";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 18:28:27 +00:00
|
|
|
if (Commands.size() == 2) {
|
2006-07-18 17:43:54 +00:00
|
|
|
// Emit two possibilitys with if/else.
|
|
|
|
O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
|
|
|
|
<< ((1 << NumBits)-1) << ") {\n"
|
|
|
|
<< Commands[1]
|
|
|
|
<< " } else {\n"
|
|
|
|
<< Commands[0]
|
|
|
|
<< " }\n\n";
|
2010-09-18 18:50:27 +00:00
|
|
|
} else if (Commands.size() == 1) {
|
|
|
|
// Emit a single possibility.
|
|
|
|
O << Commands[0] << "\n\n";
|
2006-07-18 17:43:54 +00:00
|
|
|
} else {
|
|
|
|
O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
|
|
|
|
<< ((1 << NumBits)-1) << ") {\n"
|
|
|
|
<< " default: // unreachable.\n";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:43:54 +00:00
|
|
|
// Print out all the cases.
|
|
|
|
for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
|
|
|
|
O << " case " << i << ":\n";
|
|
|
|
O << Commands[i];
|
|
|
|
O << " break;\n";
|
|
|
|
}
|
|
|
|
O << " }\n\n";
|
2006-07-18 17:18:03 +00:00
|
|
|
}
|
|
|
|
}
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:56:07 +00:00
|
|
|
// Okay, delete instructions with no operand info left.
|
2006-07-18 17:18:03 +00:00
|
|
|
for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
|
|
|
|
// Entire instruction has been emitted?
|
|
|
|
AsmWriterInst &Inst = Instructions[i];
|
2006-07-18 17:56:07 +00:00
|
|
|
if (Inst.Operands.empty()) {
|
2006-07-18 17:18:03 +00:00
|
|
|
Instructions.erase(Instructions.begin()+i);
|
2006-07-18 17:56:07 +00:00
|
|
|
--i; --e;
|
2006-07-18 17:18:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2006-07-18 17:18:03 +00:00
|
|
|
// Because this is a vector, we want to emit from the end. Reverse all of the
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
// elements in the vector.
|
|
|
|
std::reverse(Instructions.begin(), Instructions.end());
|
2010-09-29 22:32:50 +00:00
|
|
|
|
|
|
|
|
2009-09-18 18:10:19 +00:00
|
|
|
// Now that we've emitted all of the operand info that fit into 32 bits, emit
|
|
|
|
// information for those instructions that are left. This is a less dense
|
|
|
|
// encoding, but we expect the main 32-bit table to handle the majority of
|
|
|
|
// instructions.
|
2006-07-18 17:38:46 +00:00
|
|
|
if (!Instructions.empty()) {
|
|
|
|
// Find the opcode # of inline asm.
|
|
|
|
O << " switch (MI->getOpcode()) {\n";
|
|
|
|
while (!Instructions.empty())
|
|
|
|
EmitInstructions(Instructions, O);
|
Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:
case PPC::ADD: O << "add "; printOperand(MI, 0, MVT::i64); O << ", "; prin
tOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '\n
'; break;
case PPC::ADDC: O << "addc "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
case PPC::ADDE: O << "adde "; printOperand(MI, 0, MVT::i64); O << ", "; pr
intOperand(MI, 1, MVT::i64); O << ", "; printOperand(MI, 2, MVT::i64); O << '
\n'; break;
...
Emit code like this:
case PPC::ADD:
case PPC::ADDC:
case PPC::ADDE:
...
switch (MI->getOpcode()) {
case PPC::ADD: O << "add "; break;
case PPC::ADDC: O << "addc "; break;
case PPC::ADDE: O << "adde "; break;
...
}
printOperand(MI, 0, MVT::i64);
O << ", ";
printOperand(MI, 1, MVT::i64);
O << ", ";
printOperand(MI, 2, MVT::i64);
O << "\n";
break;
This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too. The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode. Thus this fixes PR448.
-Chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19755 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-22 18:38:13 +00:00
|
|
|
|
2006-07-18 17:38:46 +00:00
|
|
|
O << " }\n";
|
2009-08-08 01:32:19 +00:00
|
|
|
O << " return;\n";
|
2006-07-18 17:38:46 +00:00
|
|
|
}
|
2009-07-29 20:10:24 +00:00
|
|
|
|
2006-07-18 19:06:01 +00:00
|
|
|
O << "}\n";
|
2004-08-01 05:59:33 +00:00
|
|
|
}
|
2009-09-13 20:08:00 +00:00
|
|
|
|
|
|
|
|
|
|
|
void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
|
2010-12-13 00:23:57 +00:00
|
|
|
CodeGenTarget Target(Records);
|
2009-09-13 20:08:00 +00:00
|
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
|
|
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2009-09-14 01:26:18 +00:00
|
|
|
StringToOffsetTable StringTable;
|
2009-09-13 20:08:00 +00:00
|
|
|
O <<
|
|
|
|
"\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
|
|
|
|
"/// from the register set description. This returns the assembler name\n"
|
|
|
|
"/// for the specified register.\n"
|
|
|
|
"const char *" << Target.getName() << ClassName
|
2009-09-13 20:19:22 +00:00
|
|
|
<< "::getRegisterName(unsigned RegNo) {\n"
|
2009-09-13 20:08:00 +00:00
|
|
|
<< " assert(RegNo && RegNo < " << (Registers.size()+1)
|
|
|
|
<< " && \"Invalid register number!\");\n"
|
|
|
|
<< "\n"
|
2009-09-14 01:27:50 +00:00
|
|
|
<< " static const unsigned RegAsmOffset[] = {";
|
2009-09-13 20:08:00 +00:00
|
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
|
|
|
const CodeGenRegister &Reg = Registers[i];
|
|
|
|
|
|
|
|
std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
|
|
|
|
if (AsmName.empty())
|
|
|
|
AsmName = Reg.getName();
|
2010-09-29 22:32:50 +00:00
|
|
|
|
|
|
|
|
2009-09-14 01:27:50 +00:00
|
|
|
if ((i % 14) == 0)
|
2009-09-14 01:26:18 +00:00
|
|
|
O << "\n ";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2009-09-14 01:26:18 +00:00
|
|
|
O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
|
2009-09-13 20:08:00 +00:00
|
|
|
}
|
2009-09-14 01:26:18 +00:00
|
|
|
O << "0\n"
|
2009-09-13 20:08:00 +00:00
|
|
|
<< " };\n"
|
2009-09-14 01:26:18 +00:00
|
|
|
<< "\n";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2009-09-14 01:26:18 +00:00
|
|
|
O << " const char *AsmStrs =\n";
|
|
|
|
StringTable.EmitString(O);
|
|
|
|
O << ";\n";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2009-09-14 01:26:18 +00:00
|
|
|
O << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
|
2009-09-13 20:08:00 +00:00
|
|
|
<< "}\n";
|
|
|
|
}
|
|
|
|
|
2010-02-11 22:57:32 +00:00
|
|
|
void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) {
|
2010-12-13 00:23:57 +00:00
|
|
|
CodeGenTarget Target(Records);
|
2010-02-11 22:57:32 +00:00
|
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
|
|
|
2010-03-19 00:34:35 +00:00
|
|
|
const std::vector<const CodeGenInstruction*> &NumberedInstructions =
|
|
|
|
Target.getInstructionsByEnumValue();
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2010-02-11 22:57:32 +00:00
|
|
|
StringToOffsetTable StringTable;
|
|
|
|
O <<
|
|
|
|
"\n\n#ifdef GET_INSTRUCTION_NAME\n"
|
|
|
|
"#undef GET_INSTRUCTION_NAME\n\n"
|
|
|
|
"/// getInstructionName: This method is automatically generated by tblgen\n"
|
|
|
|
"/// from the instruction set description. This returns the enum name of the\n"
|
|
|
|
"/// specified instruction.\n"
|
|
|
|
"const char *" << Target.getName() << ClassName
|
|
|
|
<< "::getInstructionName(unsigned Opcode) {\n"
|
|
|
|
<< " assert(Opcode < " << NumberedInstructions.size()
|
|
|
|
<< " && \"Invalid instruction number!\");\n"
|
|
|
|
<< "\n"
|
|
|
|
<< " static const unsigned InstAsmOffset[] = {";
|
|
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
|
|
const CodeGenInstruction &Inst = *NumberedInstructions[i];
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2010-02-11 22:57:32 +00:00
|
|
|
std::string AsmName = Inst.TheDef->getName();
|
|
|
|
if ((i % 14) == 0)
|
|
|
|
O << "\n ";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2010-02-11 22:57:32 +00:00
|
|
|
O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
|
|
|
|
}
|
|
|
|
O << "0\n"
|
|
|
|
<< " };\n"
|
|
|
|
<< "\n";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2010-02-11 22:57:32 +00:00
|
|
|
O << " const char *Strs =\n";
|
|
|
|
StringTable.EmitString(O);
|
|
|
|
O << ";\n";
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2010-02-11 22:57:32 +00:00
|
|
|
O << " return Strs+InstAsmOffset[Opcode];\n"
|
|
|
|
<< "}\n\n#endif\n";
|
|
|
|
}
|
|
|
|
|
2011-02-26 03:09:12 +00:00
|
|
|
void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
|
|
|
|
CodeGenTarget Target(Records);
|
|
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
|
|
|
|
|
|
O << "\n#ifdef PRINT_ALIAS_INSTR\n";
|
|
|
|
O << "#undef PRINT_ALIAS_INSTR\n\n";
|
|
|
|
|
|
|
|
// Enumerate the register classes.
|
|
|
|
const std::vector<CodeGenRegisterClass> &RegisterClasses =
|
|
|
|
Target.getRegisterClasses();
|
|
|
|
|
|
|
|
O << "namespace { // Register classes\n";
|
|
|
|
O << " enum RegClass {\n";
|
|
|
|
|
|
|
|
// Emit the register enum value for each RegisterClass.
|
|
|
|
for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
|
|
|
|
if (I != 0) O << ",\n";
|
|
|
|
O << " RC_" << RegisterClasses[I].TheDef->getName();
|
|
|
|
}
|
|
|
|
|
|
|
|
O << "\n };\n";
|
|
|
|
O << "} // end anonymous namespace\n\n";
|
|
|
|
|
|
|
|
// Emit a function that returns 'true' if a regsiter is part of a particular
|
|
|
|
// register class. I.e., RAX is part of GR64 on X86.
|
|
|
|
O << "static bool regIsInRegisterClass"
|
|
|
|
<< "(unsigned RegClass, unsigned Reg) {\n";
|
|
|
|
|
|
|
|
// Emit the switch that checks if a register belongs to a particular register
|
|
|
|
// class.
|
|
|
|
O << " switch (RegClass) {\n";
|
|
|
|
O << " default: break;\n";
|
|
|
|
|
|
|
|
for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
|
|
|
|
const CodeGenRegisterClass &RC = RegisterClasses[I];
|
|
|
|
|
|
|
|
// Give the register class a legal C name if it's anonymous.
|
|
|
|
std::string Name = RC.TheDef->getName();
|
|
|
|
O << " case RC_" << Name << ":\n";
|
|
|
|
|
|
|
|
// Emit the register list now.
|
|
|
|
unsigned IE = RC.Elements.size();
|
|
|
|
if (IE == 1) {
|
|
|
|
O << " if (Reg == " << getQualifiedName(RC.Elements[0]) << ")\n";
|
|
|
|
O << " return true;\n";
|
|
|
|
} else {
|
|
|
|
O << " switch (Reg) {\n";
|
|
|
|
O << " default: break;\n";
|
|
|
|
|
|
|
|
for (unsigned II = 0; II != IE; ++II) {
|
|
|
|
Record *Reg = RC.Elements[II];
|
|
|
|
O << " case " << getQualifiedName(Reg) << ":\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
O << " return true;\n";
|
|
|
|
O << " }\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
O << " break;\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
O << " }\n\n";
|
|
|
|
O << " return false;\n";
|
|
|
|
O << "}\n\n";
|
|
|
|
|
|
|
|
// Emit the method that prints the alias instruction.
|
|
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
2010-02-11 22:57:32 +00:00
|
|
|
|
2011-02-26 03:09:12 +00:00
|
|
|
bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter");
|
|
|
|
const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr";
|
|
|
|
|
|
|
|
O << "bool " << Target.getName() << ClassName
|
|
|
|
<< "::printAliasInstr(const " << MachineInstrClassName
|
|
|
|
<< " *MI, raw_ostream &OS) {\n";
|
|
|
|
|
|
|
|
std::vector<Record*> AllInstAliases =
|
|
|
|
Records.getAllDerivedDefinitions("InstAlias");
|
|
|
|
|
|
|
|
// Create a map from the qualified name to a list of potential matches.
|
|
|
|
std::map<std::string, std::vector<CodeGenInstAlias*> > AliasMap;
|
|
|
|
for (std::vector<Record*>::iterator
|
|
|
|
I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
|
|
|
|
CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target);
|
|
|
|
const Record *R = *I;
|
|
|
|
const DagInit *DI = R->getValueAsDag("ResultInst");
|
|
|
|
const DefInit *Op = dynamic_cast<const DefInit*>(DI->getOperator());
|
|
|
|
AliasMap[getQualifiedName(Op->getDef())].push_back(Alias);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (AliasMap.empty() || !isMC) {
|
|
|
|
// FIXME: Support MachineInstr InstAliases?
|
|
|
|
O << " return true;\n";
|
|
|
|
O << "}\n\n";
|
|
|
|
O << "#endif // PRINT_ALIAS_INSTR\n";
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
O << " StringRef AsmString;\n";
|
|
|
|
O << " std::map<StringRef, unsigned> OpMap;\n";
|
|
|
|
O << " switch (MI->getOpcode()) {\n";
|
|
|
|
O << " default: return true;\n";
|
|
|
|
|
|
|
|
for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator
|
|
|
|
I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
|
|
|
|
std::vector<CodeGenInstAlias*> &Aliases = I->second;
|
|
|
|
|
|
|
|
std::map<std::string, unsigned> CondCount;
|
|
|
|
std::map<std::string, std::string> BodyMap;
|
|
|
|
|
|
|
|
std::string AsmString = "";
|
|
|
|
|
|
|
|
for (std::vector<CodeGenInstAlias*>::iterator
|
|
|
|
II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) {
|
|
|
|
const CodeGenInstAlias *CGA = *II;
|
|
|
|
AsmString = CGA->AsmString;
|
|
|
|
unsigned Indent = 8;
|
|
|
|
unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
|
|
|
|
|
|
|
|
std::string Cond;
|
|
|
|
raw_string_ostream CondO(Cond);
|
|
|
|
|
|
|
|
CondO << "if (MI->getNumOperands() == " << LastOpNo;
|
|
|
|
|
|
|
|
std::map<StringRef, unsigned> OpMap;
|
|
|
|
bool CantHandle = false;
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
|
|
|
|
const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
|
|
|
|
|
|
|
|
switch (RO.Kind) {
|
|
|
|
default: assert(0 && "unexpected InstAlias operand kind");
|
|
|
|
case CodeGenInstAlias::ResultOperand::K_Record: {
|
|
|
|
const Record *Rec = RO.getRecord();
|
|
|
|
StringRef ROName = RO.getName();
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("RegisterClass")) {
|
|
|
|
CondO << " &&\n";
|
|
|
|
CondO.indent(Indent) << "MI->getOperand(" << i << ").isReg() &&\n";
|
|
|
|
if (OpMap.find(ROName) == OpMap.end()) {
|
|
|
|
OpMap[ROName] = i;
|
|
|
|
CondO.indent(Indent)
|
|
|
|
<< "regIsInRegisterClass(RC_"
|
|
|
|
<< CGA->ResultOperands[i].getRecord()->getName()
|
|
|
|
<< ", MI->getOperand(" << i << ").getReg())";
|
|
|
|
} else {
|
|
|
|
CondO.indent(Indent)
|
|
|
|
<< "MI->getOperand(" << i
|
|
|
|
<< ").getReg() == MI->getOperand("
|
|
|
|
<< OpMap[ROName] << ").getReg()";
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
|
|
|
|
// FIXME: We need to handle these situations.
|
|
|
|
CantHandle = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CodeGenInstAlias::ResultOperand::K_Imm:
|
|
|
|
CondO << " &&\n";
|
|
|
|
CondO.indent(Indent) << "MI->getOperand(" << i << ").getImm() == ";
|
|
|
|
CondO << CGA->ResultOperands[i].getImm();
|
|
|
|
break;
|
|
|
|
case CodeGenInstAlias::ResultOperand::K_Reg:
|
|
|
|
CondO << " &&\n";
|
|
|
|
CondO.indent(Indent) << "MI->getOperand(" << i << ").getReg() == ";
|
|
|
|
CondO << Target.getName() << "::"
|
|
|
|
<< CGA->ResultOperands[i].getRegister()->getName();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (CantHandle) break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (CantHandle) continue;
|
|
|
|
|
|
|
|
CondO << ")";
|
|
|
|
|
|
|
|
std::string Body;
|
|
|
|
raw_string_ostream BodyO(Body);
|
|
|
|
|
|
|
|
BodyO << " // " << CGA->Result->getAsString() << "\n";
|
|
|
|
BodyO << " AsmString = \"" << AsmString << "\";\n";
|
|
|
|
|
|
|
|
for (std::map<StringRef, unsigned>::iterator
|
|
|
|
III = OpMap.begin(), IIE = OpMap.end(); III != IIE; ++III)
|
|
|
|
BodyO << " OpMap[\"" << III->first << "\"] = "
|
|
|
|
<< III->second << ";\n";
|
|
|
|
|
|
|
|
++CondCount[CondO.str()];
|
|
|
|
BodyMap[CondO.str()] = BodyO.str();
|
|
|
|
}
|
|
|
|
|
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std::string Code;
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raw_string_ostream CodeO(Code);
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bool EmitElse = false;
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for (std::map<std::string, unsigned>::iterator
|
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II = CondCount.begin(), IE = CondCount.end(); II != IE; ++II) {
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if (II->second != 1) continue;
|
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CodeO << " ";
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if (EmitElse) CodeO << "} else ";
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CodeO << II->first << " {\n";
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|
CodeO << BodyMap[II->first];
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EmitElse = true;
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|
}
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|
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|
if (CodeO.str().empty()) continue;
|
|
|
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O << " case " << I->first << ":\n";
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|
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|
O << CodeO.str();
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|
O << " }\n";
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|
O << " break;\n";
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|
}
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|
O << " }\n\n";
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|
|
// Code that prints the alias, replacing the operands with the ones from the
|
|
|
|
// MCInst.
|
|
|
|
O << " if (AsmString.empty()) return true;\n";
|
|
|
|
O << " std::pair<StringRef, StringRef> ASM = AsmString.split(' ');\n";
|
|
|
|
O << " OS << '\\t' << ASM.first;\n";
|
|
|
|
|
|
|
|
O << " if (!ASM.second.empty()) {\n";
|
|
|
|
O << " OS << '\\t';\n";
|
|
|
|
O << " for (StringRef::iterator\n";
|
|
|
|
O << " I = ASM.second.begin(), E = ASM.second.end(); I != E; ) {\n";
|
|
|
|
O << " if (*I == '$') {\n";
|
|
|
|
O << " StringRef::iterator Start = ++I;\n";
|
|
|
|
O << " while (I != E &&\n";
|
|
|
|
O << " ((*I >= 'a' && *I <= 'z') ||\n";
|
|
|
|
O << " (*I >= 'A' && *I <= 'Z') ||\n";
|
|
|
|
O << " (*I >= '0' && *I <= '9') ||\n";
|
|
|
|
O << " *I == '_'))\n";
|
|
|
|
O << " ++I;\n";
|
|
|
|
O << " StringRef Name(Start, I - Start);\n";
|
|
|
|
O << " printOperand(MI, OpMap[Name], OS);\n";
|
|
|
|
O << " } else {\n";
|
|
|
|
O << " OS << *I++;\n";
|
|
|
|
O << " }\n";
|
|
|
|
O << " }\n";
|
|
|
|
O << " }\n\n";
|
|
|
|
|
|
|
|
O << " return false;\n";
|
|
|
|
O << "}\n\n";
|
|
|
|
|
|
|
|
O << "#endif // PRINT_ALIAS_INSTR\n";
|
|
|
|
}
|
2009-09-13 20:08:00 +00:00
|
|
|
|
|
|
|
void AsmWriterEmitter::run(raw_ostream &O) {
|
|
|
|
EmitSourceFileHeader("Assembly Writer Source Fragment", O);
|
2010-09-29 22:32:50 +00:00
|
|
|
|
2009-09-13 20:08:00 +00:00
|
|
|
EmitPrintInstruction(O);
|
|
|
|
EmitGetRegisterName(O);
|
2010-02-11 22:57:32 +00:00
|
|
|
EmitGetInstructionName(O);
|
2011-02-26 03:09:12 +00:00
|
|
|
EmitPrintAliasInstruction(O);
|
2009-09-13 20:08:00 +00:00
|
|
|
}
|
|
|
|
|