Reenable use of TBAA during CodeGen
We had disabled use of TBAA during CodeGen (even when otherwise using AA)
because the ptrtoint/inttoptr used by CGP for address sinking caused BasicAA to
miss basic type punning that it should catch (and, thus, we'd fail to override
TBAA when we should).
However, when AA is in use during CodeGen, CGP now uses normal GEPs and
bitcasts, instead of ptrtoint/inttoptr, when doing address sinking. As a
result, BasicAA should be able to make us do the right thing in the face of
type-punning, and it seems safe to enable use of TBAA again. self-hosting seems
fine on PPC64/Linux on the P7, with TBAA enabled and -misched=shuffle.
Note: We still don't update TBAA when merging stack slots, although because
BasicAA should now catch all such cases, this is no longer a blocking issue.
Nevertheless, I plan to commit code to deal with this properly in the near
future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206093 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-12 01:26:00 +00:00
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; RUN: llc -enable-misched -misched=shuffle -enable-aa-sched-mi -use-tbaa-in-sched-mi=0 -post-RA-scheduler=0 -mcpu=ppc64 < %s | FileCheck %s
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2014-01-25 20:16:36 +00:00
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; REQUIRES: asserts
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; -misched=shuffle is NDEBUG only!
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%"class.llvm::MCOperand" = type { i8, %union.anon.110 }
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%union.anon.110 = type { i64 }
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define void @foo(i32 %v) {
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entry:
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%MCOp = alloca %"class.llvm::MCOperand", align 8
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br label %next
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; CHECK-LABEL: @foo
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next:
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%sunkaddr18 = ptrtoint %"class.llvm::MCOperand"* %MCOp to i64
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%sunkaddr19 = add i64 %sunkaddr18, 8
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%sunkaddr20 = inttoptr i64 %sunkaddr19 to double*
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store double 0.000000e+00, double* %sunkaddr20, align 8, !tbaa !1
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%sunkaddr21 = ptrtoint %"class.llvm::MCOperand"* %MCOp to i64
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%sunkaddr22 = add i64 %sunkaddr21, 8
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%sunkaddr23 = inttoptr i64 %sunkaddr22 to i32*
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store i32 %v, i32* %sunkaddr23, align 8, !tbaa !2
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ret void
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; Make sure that the 64-bit store comes first, regardless of what TBAA says
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; about the two not aliasing!
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; CHECK: li [[REG:[0-9]+]], 0
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; CHECK: std [[REG]], -[[OFF:[0-9]+]](1)
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; CHECK: stw 3, -[[OFF]](1)
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; CHECK: blr
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}
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!0 = metadata !{ metadata !"root" }
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!1 = metadata !{ metadata !"set1", metadata !0 }
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!2 = metadata !{ metadata !"set2", metadata !0 }
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