2006-05-14 22:18:28 +00:00
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//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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2006-05-14 22:18:28 +00:00
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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2014-03-22 23:51:00 +00:00
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#include "ARMTargetMachine.h"
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2012-12-03 16:50:05 +00:00
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#include "ARMFrameLowering.h"
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2007-05-16 02:01:49 +00:00
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#include "llvm/CodeGen/Passes.h"
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2011-09-27 22:14:12 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/PassManager.h"
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2010-12-05 22:04:16 +00:00
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#include "llvm/Support/CommandLine.h"
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2009-07-14 20:18:05 +00:00
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#include "llvm/Support/FormattedStream.h"
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2011-08-24 18:08:43 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2007-01-19 07:51:42 +00:00
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#include "llvm/Target/TargetOptions.h"
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2011-10-17 17:17:43 +00:00
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#include "llvm/Transforms/Scalar.h"
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2006-05-14 22:18:28 +00:00
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using namespace llvm;
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2013-03-15 18:28:25 +00:00
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static cl::opt<bool>
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DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
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cl::desc("Inhibit optimization of S->D register accesses on A15"),
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cl::init(false));
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2009-08-11 15:33:49 +00:00
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extern "C" void LLVMInitializeARMTarget() {
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2009-07-25 06:49:55 +00:00
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// Register the target.
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2014-04-01 15:19:30 +00:00
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RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
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RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
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RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
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RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
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2009-07-25 06:49:55 +00:00
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}
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2009-06-16 20:12:29 +00:00
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2011-12-20 02:50:00 +00:00
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2007-02-23 03:14:31 +00:00
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/// TargetMachine ctor - Create an ARM architecture model.
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///
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2011-07-19 06:37:02 +00:00
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ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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2011-12-02 22:16:29 +00:00
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const TargetOptions &Options,
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2011-11-16 08:38:26 +00:00
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Reloc::Model RM, CodeModel::Model CM,
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2014-03-28 14:35:30 +00:00
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CodeGenOpt::Level OL,
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bool isLittle)
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2011-12-02 22:16:29 +00:00
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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2014-03-28 14:35:30 +00:00
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Subtarget(TT, CPU, FS, isLittle, Options),
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2008-11-08 07:38:22 +00:00
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JITInfo(),
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2011-04-06 22:35:47 +00:00
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InstrItins(Subtarget.getInstrItineraryData()) {
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2013-12-18 14:18:36 +00:00
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// Default to triple-appropriate float ABI
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2011-12-02 22:16:29 +00:00
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if (Options.FloatABIType == FloatABI::Default)
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2013-12-18 09:27:33 +00:00
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this->Options.FloatABIType =
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Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
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2008-10-30 16:10:54 +00:00
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}
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2006-05-14 22:18:28 +00:00
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Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 01:37:14 +00:00
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void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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2013-01-07 21:12:13 +00:00
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// Add first the target-independent BasicTTI pass, then our ARM pass. This
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// allows the ARM pass to delegate to the target independent layer when
|
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 01:37:14 +00:00
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// appropriate.
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2013-06-19 20:51:24 +00:00
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PM.add(createBasicTargetTransformInfoPass(this));
|
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 01:37:14 +00:00
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PM.add(createARMTargetTransformInfoPass(this));
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}
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2011-12-20 02:50:00 +00:00
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void ARMTargetMachine::anchor() { }
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2013-12-09 23:56:41 +00:00
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static std::string computeDataLayout(ARMSubtarget &ST) {
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2014-03-28 14:35:30 +00:00
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std::string Ret = "";
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if (ST.isLittle())
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// Little endian.
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Ret += "e";
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else
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// Big endian.
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Ret += "E";
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2014-01-03 19:21:54 +00:00
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Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
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// Pointers are 32 bits and aligned to 32 bits.
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Ret += "-p:32:32";
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2013-12-09 23:56:41 +00:00
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2013-12-16 19:31:14 +00:00
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// On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
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// align to 32.
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if (ST.isThumb())
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Ret += "-i1:8:32-i8:8:32-i16:16:32";
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2014-03-31 18:09:10 +00:00
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// ABIs other than APCS have 64 bit integers with natural alignment.
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2013-12-17 21:28:36 +00:00
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if (!ST.isAPCS_ABI())
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Ret += "-i64:64";
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// We have 64 bits floats. The APCS ABI requires them to be aligned to 32
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// bits, others to 64 bits. We always try to align to 64 bits.
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2013-12-09 23:56:41 +00:00
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if (ST.isAPCS_ABI())
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2013-12-12 17:43:37 +00:00
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Ret += "-f64:32:64";
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2013-12-09 23:56:41 +00:00
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2013-12-10 00:37:37 +00:00
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// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
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// to 64. We always ty to give them natural alignment.
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2013-12-09 23:56:41 +00:00
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if (ST.isAPCS_ABI())
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2013-12-16 19:31:14 +00:00
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Ret += "-v64:32:64-v128:32:128";
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2013-12-09 23:56:41 +00:00
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else
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2013-12-12 17:43:37 +00:00
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Ret += "-v128:64:128";
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2013-12-09 23:56:41 +00:00
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2013-12-17 21:36:54 +00:00
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// On thumb and APCS, only try to align aggregates to 32 bits (the default is
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// 64 bits).
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if (ST.isThumb() || ST.isAPCS_ABI())
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2013-12-10 00:15:35 +00:00
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Ret += "-a:0:32";
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2013-12-09 23:56:41 +00:00
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2013-12-10 00:37:37 +00:00
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// Integer registers are 32 bits.
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2013-12-09 23:56:41 +00:00
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Ret += "-n32";
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2013-12-19 00:44:37 +00:00
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// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
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// aligned everywhere else.
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if (ST.isTargetNaCl())
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Ret += "-S128";
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else if (ST.isAAPCS_ABI())
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2013-12-09 23:56:41 +00:00
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Ret += "-S64";
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else
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Ret += "-S32";
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return Ret;
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}
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2011-07-19 06:37:02 +00:00
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ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
|
2011-12-02 22:16:29 +00:00
|
|
|
const TargetOptions &Options,
|
2011-11-16 08:38:26 +00:00
|
|
|
Reloc::Model RM, CodeModel::Model CM,
|
2014-03-28 14:35:30 +00:00
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CodeGenOpt::Level OL,
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bool isLittle)
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: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
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2011-12-02 22:16:29 +00:00
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InstrInfo(Subtarget),
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2013-12-09 23:56:41 +00:00
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DL(computeDataLayout(Subtarget)),
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2010-05-11 17:31:57 +00:00
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TLInfo(*this),
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2010-11-15 00:06:54 +00:00
|
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TSInfo(*this),
|
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 01:37:14 +00:00
|
|
|
FrameLowering(Subtarget) {
|
2013-05-13 01:16:13 +00:00
|
|
|
initAsmInfo();
|
2010-08-11 07:17:46 +00:00
|
|
|
if (!Subtarget.hasARMOps())
|
|
|
|
|
report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
|
|
|
|
|
"support ARM mode execution!");
|
2009-06-26 21:28:53 +00:00
|
|
|
}
|
|
|
|
|
|
2014-04-01 15:19:30 +00:00
|
|
|
void ARMLETargetMachine::anchor() { }
|
2014-03-28 14:35:30 +00:00
|
|
|
|
2014-04-01 15:19:30 +00:00
|
|
|
ARMLETargetMachine::
|
|
|
|
|
ARMLETargetMachine(const Target &T, StringRef TT,
|
2014-03-28 14:35:30 +00:00
|
|
|
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
|
|
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
|
|
|
CodeGenOpt::Level OL)
|
|
|
|
|
: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
|
|
|
|
|
2014-04-01 15:19:30 +00:00
|
|
|
void ARMBETargetMachine::anchor() { }
|
2014-03-28 14:35:30 +00:00
|
|
|
|
2014-04-01 15:19:30 +00:00
|
|
|
ARMBETargetMachine::
|
|
|
|
|
ARMBETargetMachine(const Target &T, StringRef TT,
|
2014-03-28 14:35:30 +00:00
|
|
|
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
|
|
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
|
|
|
CodeGenOpt::Level OL)
|
|
|
|
|
: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
|
|
|
|
|
|
2011-12-20 02:50:00 +00:00
|
|
|
void ThumbTargetMachine::anchor() { }
|
|
|
|
|
|
2011-07-19 06:37:02 +00:00
|
|
|
ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
|
|
|
|
|
StringRef CPU, StringRef FS,
|
2011-12-02 22:16:29 +00:00
|
|
|
const TargetOptions &Options,
|
2011-11-16 08:38:26 +00:00
|
|
|
Reloc::Model RM, CodeModel::Model CM,
|
2014-03-28 14:35:30 +00:00
|
|
|
CodeGenOpt::Level OL,
|
|
|
|
|
bool isLittle)
|
|
|
|
|
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
|
2009-08-15 07:59:10 +00:00
|
|
|
InstrInfo(Subtarget.hasThumb2()
|
|
|
|
|
? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
|
|
|
|
|
: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
|
2013-12-09 23:56:41 +00:00
|
|
|
DL(computeDataLayout(Subtarget)),
|
2010-05-11 17:31:57 +00:00
|
|
|
TLInfo(*this),
|
2010-11-15 00:06:54 +00:00
|
|
|
TSInfo(*this),
|
2011-01-10 12:39:04 +00:00
|
|
|
FrameLowering(Subtarget.hasThumb2()
|
|
|
|
|
? new ARMFrameLowering(Subtarget)
|
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 01:37:14 +00:00
|
|
|
: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
|
2013-05-13 01:16:13 +00:00
|
|
|
initAsmInfo();
|
2009-06-26 21:28:53 +00:00
|
|
|
}
|
|
|
|
|
|
2014-04-01 15:19:30 +00:00
|
|
|
void ThumbLETargetMachine::anchor() { }
|
2014-03-28 14:35:30 +00:00
|
|
|
|
2014-04-01 15:19:30 +00:00
|
|
|
ThumbLETargetMachine::
|
|
|
|
|
ThumbLETargetMachine(const Target &T, StringRef TT,
|
2014-03-28 14:35:30 +00:00
|
|
|
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
|
|
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
|
|
|
CodeGenOpt::Level OL)
|
|
|
|
|
: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
|
|
|
|
|
2014-04-01 15:19:30 +00:00
|
|
|
void ThumbBETargetMachine::anchor() { }
|
2014-03-28 14:35:30 +00:00
|
|
|
|
2014-04-01 15:19:30 +00:00
|
|
|
ThumbBETargetMachine::
|
|
|
|
|
ThumbBETargetMachine(const Target &T, StringRef TT,
|
2014-03-28 14:35:30 +00:00
|
|
|
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
|
|
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
|
|
|
CodeGenOpt::Level OL)
|
|
|
|
|
: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
|
|
|
|
|
|
2012-02-03 05:12:41 +00:00
|
|
|
namespace {
|
|
|
|
|
/// ARM Code Generator Pass Configuration Options.
|
|
|
|
|
class ARMPassConfig : public TargetPassConfig {
|
|
|
|
|
public:
|
2012-02-04 02:56:59 +00:00
|
|
|
ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
|
|
|
|
|
: TargetPassConfig(TM, PM) {}
|
2012-02-03 05:12:41 +00:00
|
|
|
|
|
|
|
|
ARMBaseTargetMachine &getARMTargetMachine() const {
|
|
|
|
|
return getTM<ARMBaseTargetMachine>();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const ARMSubtarget &getARMSubtarget() const {
|
|
|
|
|
return *getARMTargetMachine().getSubtargetImpl();
|
|
|
|
|
}
|
|
|
|
|
|
2014-03-10 02:09:33 +00:00
|
|
|
bool addPreISel() override;
|
|
|
|
|
bool addInstSelector() override;
|
|
|
|
|
bool addPreRegAlloc() override;
|
|
|
|
|
bool addPreSched2() override;
|
|
|
|
|
bool addPreEmitPass() override;
|
2012-02-03 05:12:41 +00:00
|
|
|
};
|
|
|
|
|
} // namespace
|
|
|
|
|
|
2012-02-04 02:56:59 +00:00
|
|
|
TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
|
|
|
return new ARMPassConfig(this, PM);
|
2012-02-03 05:12:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ARMPassConfig::addPreISel() {
|
2014-04-03 11:44:58 +00:00
|
|
|
const ARMSubtarget *Subtarget = &getARMSubtarget();
|
|
|
|
|
if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only())
|
|
|
|
|
addPass(createARMAtomicExpandPass(TM));
|
|
|
|
|
|
2014-02-18 11:17:29 +00:00
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None)
|
2013-06-19 21:07:11 +00:00
|
|
|
addPass(createGlobalMergePass(TM));
|
2006-05-14 22:18:28 +00:00
|
|
|
|
2010-07-24 21:52:08 +00:00
|
|
|
return false;
|
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2012-02-03 05:12:41 +00:00
|
|
|
bool ARMPassConfig::addInstSelector() {
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
|
2012-09-27 05:21:41 +00:00
|
|
|
|
|
|
|
|
const ARMSubtarget *Subtarget = &getARMSubtarget();
|
|
|
|
|
if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
|
|
|
|
|
TM->Options.EnableFastISel)
|
|
|
|
|
addPass(createARMGlobalBaseRegPass());
|
2006-09-04 04:14:57 +00:00
|
|
|
return false;
|
|
|
|
|
}
|
2006-09-19 15:49:25 +00:00
|
|
|
|
2012-02-03 05:12:41 +00:00
|
|
|
bool ARMPassConfig::addPreRegAlloc() {
|
2009-09-27 09:46:04 +00:00
|
|
|
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
|
2012-02-03 05:12:41 +00:00
|
|
|
if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createARMLoadStoreOptimizationPass(true));
|
2013-07-29 09:25:50 +00:00
|
|
|
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createMLxExpansionPass());
|
2013-03-15 18:28:25 +00:00
|
|
|
// Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
|
|
|
|
|
// enabled when NEON is available.
|
|
|
|
|
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
|
|
|
|
|
getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
|
|
|
|
|
addPass(createA15SDOptimizerPass());
|
|
|
|
|
}
|
2009-06-13 09:12:55 +00:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2012-02-03 05:12:41 +00:00
|
|
|
bool ARMPassConfig::addPreSched2() {
|
2009-09-30 08:53:01 +00:00
|
|
|
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
|
2011-11-16 08:38:26 +00:00
|
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
2012-03-28 22:50:56 +00:00
|
|
|
if (!getARMSubtarget().isThumb1Only()) {
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createARMLoadStoreOptimizationPass());
|
2012-03-28 22:50:56 +00:00
|
|
|
printAndVerify("After ARM load / store optimizer");
|
|
|
|
|
}
|
2013-03-27 12:38:44 +00:00
|
|
|
if (getARMSubtarget().hasNEON())
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
|
2010-11-11 20:50:14 +00:00
|
|
|
}
|
2009-09-30 08:53:01 +00:00
|
|
|
|
2009-11-06 23:52:48 +00:00
|
|
|
// Expand some pseudo instructions into multiple instructions to allow
|
|
|
|
|
// proper scheduling.
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createARMExpandPseudoPass());
|
2009-11-06 23:52:48 +00:00
|
|
|
|
2011-11-16 08:38:26 +00:00
|
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
2013-09-09 14:21:49 +00:00
|
|
|
if (!getARMSubtarget().isThumb1Only()) {
|
|
|
|
|
// in v8, IfConversion depends on Thumb instruction widths
|
2013-11-13 18:29:49 +00:00
|
|
|
if (getARMSubtarget().restrictIT() &&
|
2013-09-09 14:21:49 +00:00
|
|
|
!getARMSubtarget().prefers32BitThumb())
|
|
|
|
|
addPass(createThumb2SizeReductionPass());
|
2012-07-02 19:48:37 +00:00
|
|
|
addPass(&IfConverterID);
|
2013-09-09 14:21:49 +00:00
|
|
|
}
|
2010-06-16 07:35:02 +00:00
|
|
|
}
|
2012-02-03 05:12:41 +00:00
|
|
|
if (getARMSubtarget().isThumb2())
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createThumb2ITBlockPass());
|
2010-06-16 07:35:02 +00:00
|
|
|
|
2009-09-30 08:53:01 +00:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2012-02-03 05:12:41 +00:00
|
|
|
bool ARMPassConfig::addPreEmitPass() {
|
|
|
|
|
if (getARMSubtarget().isThumb2()) {
|
|
|
|
|
if (!getARMSubtarget().prefers32BitThumb())
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createThumb2SizeReductionPass());
|
2011-12-14 02:11:42 +00:00
|
|
|
|
|
|
|
|
// Constant island pass work on unbundled instructions.
|
2012-07-02 19:48:37 +00:00
|
|
|
addPass(&UnpackMachineBundlesID);
|
2011-12-14 02:11:42 +00:00
|
|
|
}
|
2009-07-10 01:54:42 +00:00
|
|
|
|
2014-04-02 09:03:43 +00:00
|
|
|
addPass(createARMOptimizeBarriersPass());
|
2012-07-02 19:48:31 +00:00
|
|
|
addPass(createARMConstantIslandPass());
|
2011-12-14 02:11:42 +00:00
|
|
|
|
2006-09-19 15:49:25 +00:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-06 23:43:50 +00:00
|
|
|
bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
|
|
|
|
|
JITCodeEmitter &JCE) {
|
2009-05-30 20:51:52 +00:00
|
|
|
// Machine code emitter pass for ARM.
|
|
|
|
|
PM.add(createARMJITCodeEmitterPass(*this, JCE));
|
|
|
|
|
return false;
|
|
|
|
|
}
|
