2015-04-22 21:17:00 +00:00
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \
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; RUN: | FileCheck %s
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2012-05-12 05:10:30 +00:00
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; Check that we generate new value jump, both registers, with one
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; of the registers as new.
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2015-04-22 21:17:00 +00:00
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@Reg = common global i32 0, align 4
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2012-05-12 05:10:30 +00:00
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define i32 @main() nounwind {
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entry:
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2015-04-22 21:17:00 +00:00
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; CHECK: if (cmp.gt(r{{[0-9]+}}, r{{[0-9]+}}.new)) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
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%Reg2 = alloca i32, align 4
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%0 = load i32, i32* %Reg2, align 4
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%1 = load i32, i32* @Reg, align 4
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%tobool = icmp sle i32 %0, %1
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2012-05-12 05:10:30 +00:00
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br i1 %tobool, label %if.then, label %if.else
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if.then:
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call void @bar(i32 1, i32 2)
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br label %if.end
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if.else:
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call void @baz(i32 10, i32 20)
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br label %if.end
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if.end:
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ret i32 0
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}
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declare void @bar(i32, i32)
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declare void @baz(i32, i32)
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