2009-08-02 17:32:10 +00:00
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//===-- README.txt - Notes for Blackfin Target ------------------*- org -*-===//
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* Condition codes
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** DONE Problem with asymmetric SETCC operations
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The instruction
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CC = R0 < 2
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is not symmetric - there is no R0 > 2 instruction. On the other hand, IF CC
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JUMP can take both CC and !CC as a condition. We cannot pattern-match (brcond
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(not cc), target), the DAG optimizer removes that kind of thing.
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This is handled by creating a pseudo-register NCC that aliases CC. Register
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classes JustCC and NotCC are used to control the inversion of CC.
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** DONE CC as an i32 register
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The AnyCC register class pretends to hold i32 values. It can only represent the
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values 0 and 1, but we can copy to and from the D class. This hack makes it
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possible to represent the setcc instruction without having i1 as a legal type.
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In most cases, the CC register is set by a "CC = .." or BITTST instruction, and
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then used in a conditional branch or move. The code generator thinks it is
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moving 32 bits, but the value stays in CC. In other cases, the result of a
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comparison is actually used as am i32 number, and CC will be copied to a D
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register.
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* Stack frames
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** TODO Use Push/Pop instructions
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We should use the push/pop instructions when saving callee-saved
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registers. The are smaller, and we may even use push multiple instructions.
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** TODO requiresRegisterScavenging
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We need more intelligence in determining when the scavenger is needed. We
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should keep track of:
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- Spilling D16 registers
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- Spilling AnyCC registers
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* Assembler
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** TODO Implement PrintGlobalVariable
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** TODO Remove LOAD32sym
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It's a hack combining two instructions by concatenation.
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* Inline Assembly
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2009-08-02 17:39:17 +00:00
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These are the GCC constraints from bfin/constraints.md:
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| Code | Register class | LLVM |
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|-------+-------------------------------------------+------|
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| a | P | C |
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| d | D | C |
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| z | Call clobbered P (P0, P1, P2) | X |
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| D | EvenD | X |
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| W | OddD | X |
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| e | Accu | C |
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| A | A0 | S |
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| B | A1 | S |
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| b | I | C |
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| v | B | C |
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| f | M | C |
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| c | Circular I, B, L | X |
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| C | JustCC | S |
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| t | LoopTop | X |
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| u | LoopBottom | X |
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| k | LoopCount | X |
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| x | GR | C |
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| y | RET*, ASTAT, SEQSTAT, USP | X |
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| w | ALL | C |
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| Z | The FD-PIC GOT pointer (P3) | S |
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| Y | The FD-PIC function pointer register (P1) | S |
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| q0-q7 | R0-R7 individually | |
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| qA | P0 | |
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|-------+-------------------------------------------+------|
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| Code | Constant | |
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|-------+-------------------------------------------+------|
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| J | 1<<N, N<32 | |
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| Ks3 | imm3 | |
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| Ku3 | uimm3 | |
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| Ks4 | imm4 | |
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| Ku4 | uimm4 | |
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| Ks5 | imm5 | |
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| Ku5 | uimm5 | |
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| Ks7 | imm7 | |
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| KN7 | -imm7 | |
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| Ksh | imm16 | |
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| Kuh | uimm16 | |
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| L | ~(1<<N) | |
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| M1 | 0xff | |
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| M2 | 0xffff | |
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| P0-P4 | 0-4 | |
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| PA | Macflag, not M | |
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| PB | Macflag, only M | |
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| Q | Symbol | |
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2009-08-02 17:32:10 +00:00
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** TODO Support all register classes
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* DAG combiner
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** Create test case for each Illegal SETCC case
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The DAG combiner may someimes produce illegal i16 SETCC instructions.
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*** TODO SETCC (ctlz x), 5) == const
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*** TODO SETCC (and load, const) == const
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*** DONE SETCC (zext x) == const
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*** TODO SETCC (sext x) == const
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* Instruction selection
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** TODO Better imediate constants
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Like ARM, build constants as small imm + shift.
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** TODO Implement cycle counter
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We have CYCLES and CYCLES2 registers, but the readcyclecounter intrinsic wants
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to return i64, and the code generator doesn't know how to legalize that.
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** TODO Instruction alternatives
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Some instructions come in different variants for example:
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D = D + D
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P = P + P
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Cross combinations are not allowed:
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P = D + D (bad)
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Similarly for the subreg pseudo-instructions:
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D16L = EXTRACT_SUBREG D16, bfin_subreg_lo16
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P16L = EXTRACT_SUBREG P16, bfin_subreg_lo16
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We want to take advantage of the alternative instructions. This could be done by
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changing the DAG after instruction selection.
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** Multipatterns for load/store
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We should try to identify multipatterns for load and store instructions. The
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available instruction matrix is a bit irregular.
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Loads:
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| Addr | D | P | D 16z | D 16s | D16 | D 8z | D 8s |
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|------------+---+---+-------+-------+-----+------+------|
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| P | * | * | * | * | * | * | * |
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| P++ | * | * | * | * | | * | * |
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| P-- | * | * | * | * | | * | * |
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| P+uimm5m2 | | | * | * | | | |
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| P+uimm6m4 | * | * | | | | | |
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| P+imm16 | | | | | | * | * |
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| P+imm17m2 | | | * | * | | | |
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| P+imm18m4 | * | * | | | | | |
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| P++P | * | | * | * | * | | |
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| FP-uimm7m4 | * | * | | | | | |
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| I | * | | | | * | | |
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| I++ | * | | | | * | | |
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| I-- | * | | | | * | | |
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| I++M | * | | | | | | |
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Stores:
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| Addr | D | P | D16H | D16L | D 8 |
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|------------+---+---+------+------+-----|
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| P | * | * | * | * | * |
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| P++ | * | * | | * | * |
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| P-- | * | * | | * | * |
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| P+uimm5m2 | | | | * | |
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| P+uimm6m4 | * | * | | | |
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| P+imm16 | | | | | * |
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| P+imm17m2 | | | | * | |
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| P+imm18m4 | * | * | | | |
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| P++P | * | | * | * | |
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| FP-uimm7m4 | * | * | | | |
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| I | * | | * | * | |
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| I++ | * | | * | * | |
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| I-- | * | | * | * | |
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| I++M | * | | | | |
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2009-08-02 18:27:36 +00:00
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* Workarounds and features
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Blackfin CPUs have bugs. Each model comes in a number of silicon revisions with
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different bugs. We learn about the CPU model from the -mcpu switch.
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** Interpretation of -mcpu value
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- -mcpu=bf527 refers to the latest known BF527 revision
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- -mcpu=bf527-0.2 refers to silicon rev. 0.2
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- -mcpu=bf527-any refers to all known revisions
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- -mcpu=bf527-none disables all workarounds
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The -mcpu setting affects the __SILICON_REVISION__ macro and enabled workarounds:
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| -mcpu | __SILICON_REVISION__ | Workarounds |
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|------------+----------------------+--------------------|
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| bf527 | Def Latest | Specific to latest |
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| bf527-1.3 | Def 0x0103 | Specific to 1.3 |
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| bf527-any | Def 0xffff | All bf527-x.y |
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| bf527-none | Undefined | None |
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These are the known cores and revisions:
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| Core | Silicon | Processors |
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|-------------+--------------------+-------------------------|
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| Edinburgh | 0.3, 0.4, 0.5, 0.6 | BF531 BF532 BF533 |
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| Braemar | 0.2, 0.3 | BF534 BF536 BF537 |
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| Stirling | 0.3, 0.4, 0.5 | BF538 BF539 |
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| Moab | 0.0, 0.1, 0.2 | BF542 BF544 BF548 BF549 |
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| Teton | 0.3, 0.5 | BF561 |
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| Kookaburra | 0.0, 0.1, 0.2 | BF523 BF525 BF527 |
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| Mockingbird | 0.0, 0.1 | BF522 BF524 BF526 |
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| Brodie | 0.0, 0.1 | BF512 BF514 BF516 BF518 |
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** Compiler implemented workarounds
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Most workarounds are implemented in header files and source code using the
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__ADSPBF527__ macros. A few workarounds require compiler support.
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| Anomaly | Macro | GCC Switch |
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|----------+--------------------------------+------------------|
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| Any | __WORKAROUNDS_ENABLED | |
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| 05000074 | WA_05000074 | |
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| 05000244 | __WORKAROUND_SPECULATIVE_SYNCS | -mcsync-anomaly |
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| 05000245 | __WORKAROUND_SPECULATIVE_LOADS | -mspecld-anomaly |
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| 05000257 | WA_05000257 | |
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| 05000283 | WA_05000283 | |
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| 05000312 | WA_LOAD_LCREGS | |
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| 05000315 | WA_05000315 | |
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| 05000371 | __WORKAROUND_RETS | |
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| 05000426 | __WORKAROUND_INDIRECT_CALLS | Not -micplb |
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** GCC feature switches
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| Switch | Description |
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|---------------------------+----------------------------------------|
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| -msim | Use simulator runtime |
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| -momit-leaf-frame-pointer | Omit frame pointer for leaf functions |
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| -mlow64k | |
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| -mcsync-anomaly | |
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| -mspecld-anomaly | |
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| -mid-shared-library | |
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| -mleaf-id-shared-library | |
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| -mshared-library-id= | |
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| -msep-data | Enable separate data segment |
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| -mlong-calls | Use indirect calls |
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| -mfast-fp | |
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| -mfdpic | |
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| -minline-plt | |
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| -mstack-check-l1 | Do stack checking in L1 scratch memory |
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| -mmulticore | Enable multicore support |
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| -mcorea | Build for Core A |
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| -mcoreb | Build for Core B |
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| -msdram | Build for SDRAM |
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| -micplb | Assume ICPLBs are enabled at runtime. |
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