2012-02-28 07:46:26 +00:00
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//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-08-18 02:18:07 +00:00
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// This is the top level entry point for the Mips target.
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-08-18 02:18:07 +00:00
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// Target-independent interfaces
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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2008-11-24 07:34:46 +00:00
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include "llvm/Target/Target.td"
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2007-06-06 07:42:06 +00:00
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2014-05-07 10:27:09 +00:00
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// The overall idea of the PredicateControl class is to chop the Predicates list
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// into subsets that are usually overridden independently. This allows
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// subclasses to partially override the predicates of their superclasses without
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// having to re-add all the existing predicates.
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class PredicateControl {
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// Predicates for the encoding scheme in use such as HasStdEnc
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list<Predicate> EncodingPredicates = [];
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2014-05-07 12:48:37 +00:00
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// Predicates for the GPR size such as IsGP64bit
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list<Predicate> GPRPredicates = [];
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// Predicates for the FGR size and layout such as IsFP64bit
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list<Predicate> FGRPredicates = [];
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2014-05-07 13:57:22 +00:00
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// Predicates for the instruction group membership such as ISA's and ASE's
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list<Predicate> InsnPredicates = [];
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2014-05-07 10:27:09 +00:00
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// Predicates for anything else
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list<Predicate> AdditionalPredicates = [];
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list<Predicate> Predicates = !listconcat(EncodingPredicates,
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2014-05-07 12:48:37 +00:00
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GPRPredicates,
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FGRPredicates,
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2014-05-07 13:57:22 +00:00
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InsnPredicates,
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2014-05-07 10:27:09 +00:00
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AdditionalPredicates);
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}
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// Like Requires<> but for the AdditionalPredicates list
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class AdditionalRequires<list<Predicate> preds> {
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list<Predicate> AdditionalPredicates = preds;
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}
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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// Register File, Calling Conv, Instruction Descriptions
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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include "MipsRegisterInfo.td"
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2007-08-18 02:18:07 +00:00
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include "MipsSchedule.td"
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2007-06-06 07:42:06 +00:00
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include "MipsInstrInfo.td"
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2007-08-18 02:18:07 +00:00
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include "MipsCallingConv.td"
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2007-06-06 07:42:06 +00:00
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2010-04-05 03:10:20 +00:00
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def MipsInstrInfo : InstrInfo;
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2007-08-18 02:18:07 +00:00
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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// Mips Subtarget features //
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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2014-08-08 15:47:17 +00:00
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def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
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"Disable SVR4-style position-independent code.">;
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2008-07-09 05:32:22 +00:00
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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"General Purpose Registers are 64-bit wide.">;
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2008-07-09 05:32:22 +00:00
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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2013-10-30 02:29:43 +00:00
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"Support 64-bit FP registers.">;
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2014-07-10 15:36:12 +00:00
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def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
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"Support for FPXX.">;
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2014-04-16 15:48:55 +00:00
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def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
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"IEEE 754-2008 NaN encoding.">;
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2008-07-09 05:32:22 +00:00
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def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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2011-04-15 21:51:11 +00:00
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"true", "Only supports single precision float">;
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2008-07-09 05:32:22 +00:00
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def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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"Enable o32 ABI">;
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2011-09-20 20:28:08 +00:00
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def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
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"Enable n32 ABI">;
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def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
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"Enable n64 ABI">;
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2008-07-09 05:32:22 +00:00
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def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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"Enable eabi ABI">;
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2014-07-10 13:38:23 +00:00
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def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
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"Disable odd numbered single-precision "
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"registers">;
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2010-11-08 21:42:32 +00:00
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def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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2008-07-09 05:32:22 +00:00
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"true", "Enable vector FPU instructions.">;
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2014-05-07 16:25:22 +00:00
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def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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"Mips I ISA Support [highly experimental]">;
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips II ISA Support [highly experimental]",
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[FeatureMips1]>;
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2014-05-09 13:02:27 +00:00
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def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
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"Subset of MIPS-III that is also in MIPS32 "
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"[highly experimental]">;
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2014-05-13 11:45:36 +00:00
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def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
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"Subset of MIPS-III that is also in MIPS32r2 "
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"[highly experimental]">;
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2014-05-09 13:02:27 +00:00
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def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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"MIPS III ISA Support [highly experimental]",
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[FeatureMips2, FeatureMips3_32,
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2014-05-13 11:45:36 +00:00
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FeatureMips3_32r2, FeatureGP64Bit,
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FeatureFP64Bit]>;
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2014-05-09 14:06:17 +00:00
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def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
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"Subset of MIPS-IV that is also in MIPS32 "
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"[highly experimental]">;
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2014-05-12 11:56:16 +00:00
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def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
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"Subset of MIPS-IV that is also in MIPS32r2 "
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"[highly experimental]">;
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2014-05-09 13:02:27 +00:00
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def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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"Mips4", "MIPS IV ISA Support",
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2014-05-09 14:06:17 +00:00
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[FeatureMips3, FeatureMips4_32,
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2014-05-12 11:56:16 +00:00
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FeatureMips4_32r2]>;
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2014-05-12 12:52:44 +00:00
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def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
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"Subset of MIPS-V that is also in MIPS32r2 "
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"[highly experimental]">;
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2014-05-09 13:02:27 +00:00
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def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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"MIPS V ISA Support [highly experimental]",
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2014-05-12 12:52:44 +00:00
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[FeatureMips4, FeatureMips5_32r2]>;
|
2011-04-15 21:51:11 +00:00
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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"Mips32 ISA Support",
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2014-05-09 13:02:27 +00:00
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[FeatureMips2, FeatureMips3_32,
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2014-05-12 12:41:59 +00:00
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FeatureMips4_32]>;
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2010-11-08 21:42:32 +00:00
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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2014-05-13 11:45:36 +00:00
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[FeatureMips3_32r2, FeatureMips4_32r2,
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FeatureMips5_32r2, FeatureMips32]>;
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2014-05-09 09:46:21 +00:00
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def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
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"Mips32r6",
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"Mips32r6 ISA Support [experimental]",
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[FeatureMips32r2, FeatureFP64Bit,
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FeatureNaN2008]>;
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2011-09-20 20:28:08 +00:00
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def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
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"Mips64", "Mips64 ISA Support",
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2014-05-12 11:56:16 +00:00
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[FeatureMips5, FeatureMips32]>;
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2011-09-20 20:28:08 +00:00
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def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
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"Mips64r2", "Mips64r2 ISA Support",
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[FeatureMips64, FeatureMips32r2]>;
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2014-05-09 09:46:21 +00:00
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def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
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"Mips64r6",
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"Mips64r6 ISA Support [experimental]",
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2014-05-12 15:12:45 +00:00
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[FeatureMips32r6, FeatureMips64r2,
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FeatureNaN2008]>;
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2007-06-06 07:42:06 +00:00
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2012-05-16 22:19:56 +00:00
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def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
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"Mips16 mode">;
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2012-09-21 23:41:49 +00:00
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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"Mips DSP-R2 ASE", [FeatureDSP]>;
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2013-08-13 20:54:07 +00:00
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def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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2013-02-05 09:30:03 +00:00
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def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
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"microMips mode">;
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2014-03-20 11:51:58 +00:00
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def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
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"true", "Octeon cnMIPS Support",
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[FeatureMips64r2]>;
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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// Mips processors supported.
|
2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MipsGenericItineraries, Features>;
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2014-05-07 16:25:22 +00:00
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def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
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def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
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2014-02-20 14:58:19 +00:00
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def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
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def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
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2014-05-09 09:46:21 +00:00
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def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
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2014-05-07 16:25:22 +00:00
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def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
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2014-04-03 12:13:36 +00:00
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def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
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2014-05-07 16:25:22 +00:00
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def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
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2014-02-20 14:58:19 +00:00
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def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
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def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
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2014-05-09 09:46:21 +00:00
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def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
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2014-02-20 14:58:19 +00:00
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def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
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2014-03-20 11:51:58 +00:00
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def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
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2010-11-08 21:42:32 +00:00
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2012-08-17 20:16:42 +00:00
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def MipsAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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2013-08-01 09:25:27 +00:00
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let MnemonicContainsDot = 1;
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2012-08-17 20:16:42 +00:00
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}
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def MipsAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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// Recognize hard coded registers.
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string RegisterPrefix = "$";
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}
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2007-06-06 07:42:06 +00:00
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def Mips : Target {
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let InstructionSet = MipsInstrInfo;
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2012-08-17 20:16:42 +00:00
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let AssemblyParsers = [MipsAsmParser];
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let AssemblyParserVariants = [MipsAsmParserVariant];
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2007-06-06 07:42:06 +00:00
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}
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