2012-02-18 12:03:15 +00:00
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//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
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2005-04-21 23:30:14 +00:00
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//
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2004-02-25 19:28:19 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-02-25 19:28:19 +00:00
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//===----------------------------------------------------------------------===//
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//
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2008-02-10 18:45:23 +00:00
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// This file contains the SPARC implementation of the TargetRegisterInfo class.
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2004-02-25 19:28:19 +00:00
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//
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//===----------------------------------------------------------------------===//
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2006-02-05 05:50:24 +00:00
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#include "SparcRegisterInfo.h"
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2012-03-17 18:46:09 +00:00
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#include "Sparc.h"
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2013-05-29 04:46:31 +00:00
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#include "SparcMachineFunctionInfo.h"
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2006-02-05 05:50:24 +00:00
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#include "SparcSubtarget.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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2004-04-02 20:53:37 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/Type.h"
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2013-05-19 20:07:20 +00:00
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#include "llvm/Support/CommandLine.h"
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2009-07-11 20:10:48 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2006-11-27 23:37:22 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2011-06-27 18:32:37 +00:00
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2014-04-22 02:03:14 +00:00
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using namespace llvm;
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2011-06-27 18:32:37 +00:00
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#define GET_REGINFO_TARGET_DESC
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2011-06-24 01:44:41 +00:00
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#include "SparcGenRegisterInfo.inc"
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2011-06-27 18:32:37 +00:00
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2013-05-19 20:07:20 +00:00
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static cl::opt<bool>
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ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
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cl::desc("Reserve application registers (%g2-%g4)"));
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2015-03-12 05:55:26 +00:00
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SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
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2004-02-25 19:28:19 +00:00
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2014-04-04 05:16:06 +00:00
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const MCPhysReg*
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SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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2013-08-23 02:25:47 +00:00
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return CSR_SaveList;
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}
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2015-03-11 22:42:13 +00:00
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const uint32_t *
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SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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2013-08-23 02:25:47 +00:00
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return CSR_RegMask;
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2006-05-18 00:12:58 +00:00
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}
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2013-09-05 05:32:16 +00:00
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const uint32_t*
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SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
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return RTCSR_RegMask;
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}
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2007-02-19 21:49:54 +00:00
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BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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2015-03-12 05:55:26 +00:00
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const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
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2011-06-09 16:56:59 +00:00
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// FIXME: G1 reserved for now for large imm generation by frame code.
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Reserved.set(SP::G1);
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2013-05-19 20:07:20 +00:00
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2013-06-04 18:33:25 +00:00
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// G1-G4 can be used in applications.
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2013-05-19 20:07:20 +00:00
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if (ReserveAppRegisters) {
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Reserved.set(SP::G2);
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Reserved.set(SP::G3);
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Reserved.set(SP::G4);
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}
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2013-06-04 18:33:25 +00:00
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// G5 is not reserved in 64 bit mode.
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2013-05-19 20:07:20 +00:00
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if (!Subtarget.is64Bit())
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Reserved.set(SP::G5);
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2007-02-19 21:49:54 +00:00
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Reserved.set(SP::O6);
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Reserved.set(SP::I6);
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Reserved.set(SP::I7);
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Reserved.set(SP::G0);
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Reserved.set(SP::G6);
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Reserved.set(SP::G7);
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2013-08-25 17:03:02 +00:00
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// Unaliased double registers are not available in non-V9 targets.
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if (!Subtarget.isV9()) {
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for (unsigned n = 0; n != 16; ++n) {
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for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
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Reserved.set(*AI);
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}
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}
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2007-02-19 21:49:54 +00:00
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return Reserved;
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}
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2013-04-02 04:08:54 +00:00
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const TargetRegisterClass*
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SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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2015-03-12 05:55:26 +00:00
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const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
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2013-04-02 04:08:54 +00:00
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return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
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}
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2013-09-02 18:32:45 +00:00
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static void replaceFI(MachineFunction &MF,
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MachineBasicBlock::iterator II,
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MachineInstr &MI,
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DebugLoc dl,
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unsigned FIOperandNum, int Offset,
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unsigned FramePtr)
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{
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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2013-11-24 20:23:25 +00:00
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return;
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}
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2014-08-05 02:39:49 +00:00
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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2013-11-24 20:23:25 +00:00
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// FIXME: it would be better to scavenge a register here instead of
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// reserving G1 all of the time.
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if (Offset >= 0) {
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// Emit nonnegaive immediates with sethi + or.
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// sethi %hi(Offset), %g1
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// add %g1, %fp, %g1
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// Insert G1+%lo(offset) into the user.
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HI22(Offset));
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2013-09-02 18:32:45 +00:00
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(FramePtr);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
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2013-11-24 20:23:25 +00:00
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
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return;
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2013-09-02 18:32:45 +00:00
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}
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2013-11-24 20:23:25 +00:00
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// Emit Negative numbers with sethi + xor
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// sethi %hix(Offset), %g1
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// xor %g1, %lox(offset), %g1
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// add %g1, %fp, %g1
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// Insert: G1 + 0 into the user.
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HIX22(Offset));
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
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.addReg(SP::G1).addImm(LOX10(Offset));
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(FramePtr);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
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2013-09-02 18:32:45 +00:00
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}
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2010-08-26 23:32:16 +00:00
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void
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2009-10-07 17:12:56 +00:00
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SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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2013-01-31 20:02:54 +00:00
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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2007-05-01 09:13:03 +00:00
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assert(SPAdj == 0 && "Unexpected");
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2004-04-02 20:53:37 +00:00
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MachineInstr &MI = *II;
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2009-02-13 02:31:35 +00:00
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DebugLoc dl = MI.getDebugLoc();
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2013-01-31 20:02:54 +00:00
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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2004-04-02 20:53:37 +00:00
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2004-04-06 22:10:22 +00:00
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// Addressable stack objects are accessed using neg. offsets from %fp
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2004-08-14 22:57:22 +00:00
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MachineFunction &MF = *MI.getParent()->getParent();
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2015-03-12 05:55:26 +00:00
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const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
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2013-04-06 21:38:57 +00:00
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int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(FIOperandNum + 1).getImm() +
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Subtarget.getStackPointerBias();
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2013-05-29 04:46:31 +00:00
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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2013-06-01 04:51:18 +00:00
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unsigned FramePtr = SP::I6;
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if (FuncInfo->isLeafProc()) {
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2013-06-04 18:33:25 +00:00
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// Use %sp and adjust offset if needed.
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2013-06-01 04:51:18 +00:00
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FramePtr = SP::O6;
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int stackSize = MF.getFrameInfo()->getStackSize();
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Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
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}
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2013-09-02 18:32:45 +00:00
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if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
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if (MI.getOpcode() == SP::STQFri) {
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2015-03-12 05:55:26 +00:00
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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2013-09-02 18:32:45 +00:00
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unsigned SrcReg = MI.getOperand(2).getReg();
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unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
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unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
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MachineInstr *StMI =
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
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.addReg(FramePtr).addImm(0).addReg(SrcEvenReg);
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replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr);
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MI.setDesc(TII.get(SP::STDFri));
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MI.getOperand(2).setReg(SrcOddReg);
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Offset += 8;
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} else if (MI.getOpcode() == SP::LDQFri) {
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2015-03-12 05:55:26 +00:00
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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2013-09-02 18:32:45 +00:00
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
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unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
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MachineInstr *StMI =
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
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.addReg(FramePtr).addImm(0);
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replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr);
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MI.setDesc(TII.get(SP::LDDFri));
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MI.getOperand(0).setReg(DestOddReg);
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Offset += 8;
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}
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Reserve G1 for frame offset stuff and use it to handle large stack frames.
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:56:31 +00:00
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}
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2013-09-02 18:32:45 +00:00
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replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr);
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2004-02-25 19:28:19 +00:00
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}
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2009-11-12 21:00:03 +00:00
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unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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2009-09-08 12:47:30 +00:00
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return SP::I6;
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2006-03-23 18:12:57 +00:00
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}
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