llvm-6502/test/CodeGen/ARM/str_pre-2.ll

; RUN: llc < %s -mtriple=armv6-linux-gnu | FileCheck %s

@b = external global i64*

define i64 @t(i64 %a) nounwind readonly {
entry:
; CHECK: push {r4, r5, lr}
; CHECK: pop {r4, r5, pc}
        call void asm sideeffect "", "~{r4},~{r5}"() nounwind
	%0 = load i64** @b, align 4
	%1 = load i64* %0, align 4
	%2 = mul i64 %1, %a
	ret i64 %2
}
Fix test that depends on register allocation. The test is really checking the prolog/epilog load/store multiple formation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158328 91177308-0d34-0410-b5e6-96231b3b80d8 2012-06-11 21:14:28 +00:00			`; RUN: llc < %s -mtriple=armv6-linux-gnu \| FileCheck %s`
Fold preceding / trailing base inc / dec into the single load / store as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-03 06:14:58 +00:00
			`@b = external global i64*`

			`define i64 @t(i64 %a) nounwind readonly {`
			`entry:`
Fix test that depends on register allocation. The test is really checking the prolog/epilog load/store multiple formation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158328 91177308-0d34-0410-b5e6-96231b3b80d8 2012-06-11 21:14:28 +00:00			`; CHECK: push {r4, r5, lr}`
			`; CHECK: pop {r4, r5, pc}`
			`call void asm sideeffect "", "~{r4},~{r5}"() nounwind`
Fold preceding / trailing base inc / dec into the single load / store as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-03 06:14:58 +00:00			`%0 = load i64** @b, align 4`
			`%1 = load i64* %0, align 4`
			`%2 = mul i64 %1, %a`
			`ret i64 %2`
			`}`