llvm-6502/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt

# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}

# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0|
# -------------------------------------------------------------------------------------------------
#
# if d == n || d == t || d == t2 then UNPREDICTABLE
mc-input.txt:1:1: warning: invalid instruction encoding
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-14 19:13:28 +00:00			`# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 \|& grep {invalid instruction encoding}`

			`# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)`
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-09 20:55:18 +00:00			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-14 19:13:28 +00:00			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 1: 1: 0\| 1: 0: 0: 0\| 1: 1: 0: 0\| 0: 0: 1: 0\| 0: 1: 1: 1\| 1: 0: 0: 0\| 0: 1: 1: 1\| 1: 0: 0: 0\|`
			`# -------------------------------------------------------------------------------------------------`
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-09 20:55:18 +00:00			`#`
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-14 19:13:28 +00:00			`# if d == n \|\| d == t \|\| d == t2 then UNPREDICTABLE`
			`mc-input.txt:1:1: warning: invalid instruction encoding`