[SystemZ] Add CodeGen support for integer vector types
This the first of a series of patches to add CodeGen support exploiting
the instructions of the z13 vector facility. This patch adds support
for the native integer vector types (v16i8, v8i16, v4i32, v2i64).
When the vector facility is present, we default to the new vector ABI.
This is characterized by two major differences:
- Vector types are passed/returned in vector registers
(except for unnamed arguments of a variable-argument list function).
- Vector types are at most 8-byte aligned.
The reason for the choice of 8-byte vector alignment is that the hardware
is able to efficiently load vectors at 8-byte alignment, and the ABI only
guarantees 8-byte alignment of the stack pointer, so requiring any higher
alignment for vectors would require dynamic stack re-alignment code.
However, for compatibility with old code that may use vector types, when
*not* using the vector facility, the old alignment rules (vector types
are naturally aligned) remain in use.
These alignment rules are not only implemented at the C language level
(implemented in clang), but also at the LLVM IR level. This is done
by selecting a different DataLayout string depending on whether the
vector ABI is in effect or not.
Based on a patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236521 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:25:42 +00:00
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; Test vector addition.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a v16i8 addition.
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define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vab %v24, %v26, %v28
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; CHECK: br %r14
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%ret = add <16 x i8> %val1, %val2
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ret <16 x i8> %ret
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}
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; Test a v8i16 addition.
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define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vah %v24, %v26, %v28
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; CHECK: br %r14
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%ret = add <8 x i16> %val1, %val2
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ret <8 x i16> %ret
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}
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; Test a v4i32 addition.
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define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vaf %v24, %v26, %v28
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; CHECK: br %r14
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%ret = add <4 x i32> %val1, %val2
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ret <4 x i32> %ret
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}
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; Test a v2i64 addition.
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define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vag %v24, %v26, %v28
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; CHECK: br %r14
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%ret = add <2 x i64> %val1, %val2
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ret <2 x i64> %ret
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}
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2015-05-05 19:26:48 +00:00
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; Test a v2f64 addition.
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define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
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<2 x double> %val2) {
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; CHECK-LABEL: f5:
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; CHECK: vfadb %v24, %v26, %v28
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; CHECK: br %r14
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%ret = fadd <2 x double> %val1, %val2
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ret <2 x double> %ret
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}
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2015-05-05 19:28:34 +00:00
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; Test an f64 addition that uses vector registers.
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define double @f6(<2 x double> %val1, <2 x double> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: wfadb %f0, %v24, %v26
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; CHECK: br %r14
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%scalar1 = extractelement <2 x double> %val1, i32 0
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%scalar2 = extractelement <2 x double> %val2, i32 0
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%ret = fadd double %scalar1, %scalar2
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ret double %ret
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}
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