llvm-6502/test/CodeGen/Thumb/ispositive.ll

; RUN: llvm-as < %s | llc -march=thumb | FileCheck %s

define i32 @test1(i32 %X) {
entry:
; CHECK: test1:
; CHECK: lsrs r0, r0, #31
        icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
        zext i1 %0 to i32               ; <i32>:1 [#uses=1]
        ret i32 %1
}
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-11 06:43:01 +00:00			`; RUN: llvm-as < %s \| llc -march=thumb \| FileCheck %s`
Move thumb and thumb2 tests into separate directories. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74068 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-24 06:36:07 +00:00
			`define i32 @test1(i32 %X) {`
			`entry:`
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-11 06:43:01 +00:00			`; CHECK: test1:`
			`; CHECK: lsrs r0, r0, #31`
Move thumb and thumb2 tests into separate directories. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74068 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-24 06:36:07 +00:00			`icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]`
			`zext i1 %0 to i32 ; <i32>:1 [#uses=1]`
			`ret i32 %1`
			`}`