llvm-6502/test/CodeGen/ARM/fnmul.ll

; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep vnmul.f64
; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math | grep vmul.f64


define double @t1(double %a, double %b) {
entry:
        %tmp2 = fsub double -0.000000e+00, %a            ; <double> [#uses=1]
        %tmp4 = fmul double %tmp2, %b            ; <double> [#uses=1]
        ret double %tmp4
}
Use Unified Assembly Syntax for the ARM backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8 2009-11-09 00:11:35 +00:00			`; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 \| grep vnmul.f64`
			`; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math \| grep vmul.f64`
match a reassociated form of fnmul git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36659 91177308-0d34-0410-b5e6-96231b3b80d8 2007-05-03 00:31:40 +00:00

			`define double @t1(double %a, double %b) {`
			`entry:`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-04 22:49:04 +00:00			`%tmp2 = fsub double -0.000000e+00, %a ; <double> [#uses=1]`
			`%tmp4 = fmul double %tmp2, %b ; <double> [#uses=1]`
match a reassociated form of fnmul git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36659 91177308-0d34-0410-b5e6-96231b3b80d8 2007-05-03 00:31:40 +00:00			`ret double %tmp4`
			`}`