llvm-6502/test/CodeGen/X86/vec_set-C.ll

; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep mov | count 1
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | grep movd

define <2 x i64> @t1(i64 %x) nounwind  {
	%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
	ret <2 x i64> %tmp8
}
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8 2008-05-08 00:57:18 +00:00			`; RUN: llvm-as < %s \| llc -march=x86 -mattr=+sse2 \| grep movq`
Handle a few more cases of folding load i64 into xmm and zero top bits. Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8 2008-05-09 21:53:03 +00:00			`; RUN: llvm-as < %s \| llc -march=x86 -mattr=+sse2 \| grep mov \| count 1`
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8 2008-05-08 00:57:18 +00:00			`; RUN: llvm-as < %s \| llc -march=x86-64 -mattr=+sse2 \| grep movd`

			`define <2 x i64> @t1(i64 %x) nounwind {`
			`%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0`
			`ret <2 x i64> %tmp8`
			`}`