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llvm-6502/test/CodeGen/X86/ins_subreg_coalesce-1.ll

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llvm/test/CodeGen/X86: Update tests with -mattr=-bmi not to take BMI, corresponding to Craig's r189742. AMD Piledriver builder detected failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-02 12:00:46 +00:00
; RUN: llc < %s -march=x86 -mattr=-bmi | FileCheck %s
- More aggressively coalescing away copies whose source is defined by an implicit_def. - Added insert_subreg coalescing support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49448 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-09 20:57:25 +00:00
Enable i16 to i32 promotion by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 08:30:49 +00:00
define fastcc i32 @t() nounwind {
- More aggressively coalescing away copies whose source is defined by an implicit_def. - Added insert_subreg coalescing support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49448 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-09 20:57:25 +00:00
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 06:24:09 +00:00
; CHECK-LABEL: t:
Enable i16 to i32 promotion by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 08:30:49 +00:00
; CHECK: movzwl 0, %eax
; CHECK: orl $2, %eax
; CHECK: movw %ax, 0
; CHECK: shrl $3, %eax
; CHECK: andl $1, %eax
- More aggressively coalescing away copies whose source is defined by an implicit_def. - Added insert_subreg coalescing support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49448 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-09 20:57:25 +00:00
br i1 false, label %UnifiedReturnBlock, label %bb4
bb4: ; preds = %entry
br i1 false, label %bb17, label %bb22
bb17: ; preds = %bb4
ret i32 1
bb22: ; preds = %bb4
br i1 true, label %walkExprTree.exit, label %bb4.i
bb4.i: ; preds = %bb22
ret i32 0
walkExprTree.exit: ; preds = %bb22
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00
%tmp83 = load i16, i16* null, align 4 ; <i16> [#uses=1]
- More aggressively coalescing away copies whose source is defined by an implicit_def. - Added insert_subreg coalescing support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49448 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-09 20:57:25 +00:00
%tmp84 = or i16 %tmp83, 2 ; <i16> [#uses=2]
store i16 %tmp84, i16* null, align 4
%tmp98993 = zext i16 %tmp84 to i32 ; <i32> [#uses=1]
%tmp1004 = lshr i32 %tmp98993, 3 ; <i32> [#uses=1]
%tmp100.lobit5 = and i32 %tmp1004, 1 ; <i32> [#uses=1]
ret i32 %tmp100.lobit5
UnifiedReturnBlock: ; preds = %entry
ret i32 0
}
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