llvm-6502/test/CodeGen/ARM/fast-isel-deadcode.ll

; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB

; Target-specific selector can't properly handle the double because it isn't
; being passed via a register, so the materialized arguments become dead code.

define i32 @main(i32 %argc, i8** %argv) nounwind {
entry:
; THUMB: main
  call void @printArgsNoRet(i32 1, float 0x4000CCCCC0000000, i8 signext 99, double 4.100000e+00)
; THUMB: blx _printArgsNoRet
; THUMB-NOT: ldr
; THUMB-NOT: vldr
; THUMB-NOT: vmov
; THUMB-NOT: ldr
; THUMB-NOT: sxtb
; THUMB: movs r0, #0
; THUMB: movt r0, #0
; THUMB: pop
  ret i32 0
}

declare void @printArgsNoRet(i32 %a1, float %a2, i8 signext %a3, double %a4)
Fix ARM FastISel tests, as a first step to enabling ARM FastISel ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-14 16:26:38 +00:00			`; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios \| FileCheck %s --check-prefix=THUMB`
If fast-isel fails, remove dead instructions generated during the failed attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145425 91177308-0d34-0410-b5e6-96231b3b80d8 2011-11-29 19:40:47 +00:00
			`; Target-specific selector can't properly handle the double because it isn't`
			`; being passed via a register, so the materialized arguments become dead code.`

			`define i32 @main(i32 %argc, i8** %argv) nounwind {`
			`entry:`
			`; THUMB: main`
			`call void @printArgsNoRet(i32 1, float 0x4000CCCCC0000000, i8 signext 99, double 4.100000e+00)`
			`; THUMB: blx _printArgsNoRet`
			`; THUMB-NOT: ldr`
			`; THUMB-NOT: vldr`
			`; THUMB-NOT: vmov`
			`; THUMB-NOT: ldr`
			`; THUMB-NOT: sxtb`
			`; THUMB: movs r0, #0`
			`; THUMB: movt r0, #0`
Reapply r146997, "Heed spill slot alignment on ARM." Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147579 91177308-0d34-0410-b5e6-96231b3b80d8 2012-01-05 00:26:57 +00:00			`; THUMB: pop`
If fast-isel fails, remove dead instructions generated during the failed attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145425 91177308-0d34-0410-b5e6-96231b3b80d8 2011-11-29 19:40:47 +00:00			`ret i32 0`
			`}`

			`declare void @printArgsNoRet(i32 %a1, float %a2, i8 signext %a3, double %a4)`