llvm-6502/lib/Target/ARM/CMakeLists.txt

set(LLVM_TARGET_DEFINITIONS ARM.td)

tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(ARMGenRegisterNames.inc -gen-register-enums)
tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
tablegen(ARMGenInstrNames.inc -gen-instr-enums)
tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
tablegen(ARMGenCodeEmitter.inc -gen-emitter)
tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
tablegen(ARMGenDAGISel.inc -gen-dag-isel)
tablegen(ARMGenCallingConv.inc -gen-callingconv)
tablegen(ARMGenSubtarget.inc -gen-subtarget)

add_llvm_target(ARMCodeGen
  ARMBaseInstrInfo.cpp
  ARMBaseRegisterInfo.cpp
  ARMCodeEmitter.cpp
  ARMConstantIslandPass.cpp
  ARMConstantPoolValue.cpp
  ARMInstrInfo.cpp
  ARMISelDAGToDAG.cpp
  ARMISelLowering.cpp
  ARMJITInfo.cpp
  ARMLoadStoreOptimizer.cpp
  ARMRegisterInfo.cpp
  ARMSubtarget.cpp
  ARMMCAsmInfo.cpp
  ARMTargetMachine.cpp
  NEONPreAllocPass.cpp
  Thumb1InstrInfo.cpp
  Thumb1RegisterInfo.cpp
  Thumb2ITBlockPass.cpp
  Thumb2InstrInfo.cpp
  Thumb2RegisterInfo.cpp
  Thumb2SizeReduction.cpp
  )

target_link_libraries (LLVMARMCodeGen LLVMSelectionDAG)
CMake: Builds all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-26 04:40:32 +00:00			`set(LLVM_TARGET_DEFINITIONS ARM.td)`

			`tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)`
			`tablegen(ARMGenRegisterNames.inc -gen-register-enums)`
			`tablegen(ARMGenRegisterInfo.inc -gen-register-desc)`
			`tablegen(ARMGenInstrNames.inc -gen-instr-enums)`
			`tablegen(ARMGenInstrInfo.inc -gen-instr-desc)`
			`tablegen(ARMGenCodeEmitter.inc -gen-emitter)`
			`tablegen(ARMGenAsmWriter.inc -gen-asm-writer)`
			`tablegen(ARMGenDAGISel.inc -gen-dag-isel)`
Use CallConvLower.h and TableGen descriptions of the calling conventions for ARM. Patch by Sandeep Patel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8 2009-04-17 19:07:39 +00:00			`tablegen(ARMGenCallingConv.inc -gen-callingconv)`
CMake: Builds all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-26 04:40:32 +00:00			`tablegen(ARMGenSubtarget.inc -gen-subtarget)`

CMake: Turned some libraries into partially linked objects. Corrected names of LLVMCore and ARMCodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57943 91177308-0d34-0410-b5e6-96231b3b80d8 2008-10-22 02:51:53 +00:00			`add_llvm_target(ARMCodeGen`
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-08 16:09:28 +00:00			`ARMBaseInstrInfo.cpp`
Fix cmake build. Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75035 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-08 20:13:41 +00:00			`ARMBaseRegisterInfo.cpp`
CMake: Builds all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-26 04:40:32 +00:00			`ARMCodeEmitter.cpp`
			`ARMConstantIslandPass.cpp`
			`ARMConstantPoolValue.cpp`
			`ARMInstrInfo.cpp`
			`ARMISelDAGToDAG.cpp`
			`ARMISelLowering.cpp`
			`ARMJITInfo.cpp`
			`ARMLoadStoreOptimizer.cpp`
			`ARMRegisterInfo.cpp`
			`ARMSubtarget.cpp`
Forgot to update some CMakeLists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79780 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-22 22:20:11 +00:00			`ARMMCAsmInfo.cpp`
CMake: Builds all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-26 04:40:32 +00:00			`ARMTargetMachine.cpp`
Add a new pre-allocation pass to assign adjacent registers for Neon instructions that have that constraint. This is currently just assigning a fixed set of registers, and it only handles VLDn for n=2,3,4 with DPR registers. I'm going to expand it to handle more operations next; we can make it smarter once everything is working correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78256 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-05 23:12:45 +00:00			`NEONPreAllocPass.cpp`
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74731 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-02 22:18:33 +00:00			`Thumb1InstrInfo.cpp`
			`Thumb1RegisterInfo.cpp`
Add Thumb2ITBlockPass.cpp to CMakeLists.txt, fixing the cmake build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75246 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-10 08:31:50 +00:00			`Thumb2ITBlockPass.cpp`
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74731 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-02 22:18:33 +00:00			`Thumb2InstrInfo.cpp`
			`Thumb2RegisterInfo.cpp`
Update CMake git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78475 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-08 17:03:13 +00:00			`Thumb2SizeReduction.cpp`
CMake: Builds all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-26 04:40:32 +00:00			`)`
CMake build fixes, from Xerxes Ranby git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74720 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-02 18:53:52 +00:00
			`target_link_libraries (LLVMARMCodeGen LLVMSelectionDAG)`