6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-06 21:05:51 +00:00
Code Issues Projects Releases Wiki Activity
f33a30cdd0
llvm-6502/test/CodeGen/R600/load64.ll

31 lines
1.1 KiB
LLVM
Raw Normal View History

R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 17:11:46 +00:00
; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
R600/SI: Add initial double precision support for SI Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186177 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:14:56 +00:00
; load a f64 value from the global address space.
R600/SI: Minor improvements to test. Use CHECK-LABEL, add an i64 version, check store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-14 00:38:04 +00:00
; CHECK-LABEL: @load_f64:
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 02:35:51 +00:00
; CHECK: BUFFER_LOAD_DWORDX2 v[{{[0-9]+:[0-9]+}}]
R600/SI: Minor improvements to test. Use CHECK-LABEL, add an i64 version, check store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-14 00:38:04 +00:00
; CHECK: BUFFER_STORE_DWORDX2 v[{{[0-9]+:[0-9]+}}]
R600/SI: Add initial double precision support for SI Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186177 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:14:56 +00:00
define void @load_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
R600/SI: Minor improvements to test. Use CHECK-LABEL, add an i64 version, check store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-14 00:38:04 +00:00
%1 = load double addrspace(1)* %in
store double %1, double addrspace(1)* %out
ret void
}
; CHECK-LABEL: @load_i64:
; CHECK: BUFFER_LOAD_DWORDX2 v[{{[0-9]+:[0-9]+}}]
; CHECK: BUFFER_STORE_DWORDX2 v[{{[0-9]+:[0-9]+}}]
define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
%tmp = load i64 addrspace(1)* %in
store i64 %tmp, i64 addrspace(1)* %out, align 8
R600/SI: Add initial double precision support for SI Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186177 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:14:56 +00:00
ret void
}
; Load a f64 value from the constant address space.
R600/SI: Minor improvements to test. Use CHECK-LABEL, add an i64 version, check store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-14 00:38:04 +00:00
; CHECK-LABEL: @load_const_addrspace_f64:
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 02:35:51 +00:00
; CHECK: S_LOAD_DWORDX2 s[{{[0-9]+:[0-9]+}}]
R600/SI: Minor improvements to test. Use CHECK-LABEL, add an i64 version, check store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-14 00:38:04 +00:00
; CHECK: BUFFER_STORE_DWORDX2 v[{{[0-9]+:[0-9]+}}]
R600/SI: Add initial double precision support for SI Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186177 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:14:56 +00:00
define void @load_const_addrspace_f64(double addrspace(1)* %out, double addrspace(2)* %in) {
%1 = load double addrspace(2)* %in
store double %1, double addrspace(1)* %out
ret void
}
Reference in New Issue Copy Permalink