llvm-6502/test/CodeGen/PTX/bra.ll

; RUN: llc < %s -march=ptx32 | FileCheck %s

define ptx_device void @test_bra_direct() {
; CHECK: bra $L__BB0_1;
entry:
	br label %loop
loop:
	br label %loop
}

define ptx_device i32 @test_bra_cond_direct(i32 %x, i32 %y) {
entry:
; CHECK: setp.le.u32 p0, r[[R0:[0-9]+]], r[[R1:[0-9]+]]
	%p = icmp ugt i32 %x, %y
; CHECK-NEXT: @p0 bra
; CHECK-NOT: bra
	br i1 %p, label %clause.if, label %clause.else
clause.if:
; CHECK: mov.u32 r{{[0-9]+}}, r[[R0]]
	ret i32 %x
clause.else:
; CHECK: mov.u32 r{{[0-9]+}}, r[[R1]]
	ret i32 %y
}
PTX: Add intrinsics to list of built-in intrinsics, which allows them to be used by Clang. To help Clang integration, the PTX target has been split into two targets: ptx32 and ptx64, depending on the desired pointer size. - Add GCCBuiltin class to all intrinsics - Split PTX target into ptx32 and ptx64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129851 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-20 15:37:17 +00:00			`; RUN: llc < %s -march=ptx32 \| FileCheck %s`
ptx: add unconditional and conditional branch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127873 91177308-0d34-0410-b5e6-96231b3b80d8 2011-03-18 11:08:52 +00:00
			`define ptx_device void @test_bra_direct() {`
			`; CHECK: bra $L__BB0_1;`
			`entry:`
			`br label %loop`
			`loop:`
			`br label %loop`
			`}`

			`define ptx_device i32 @test_bra_cond_direct(i32 %x, i32 %y) {`
			`entry:`
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8 2011-06-23 18:10:13 +00:00			`; CHECK: setp.le.u32 p0, r[[R0:[0-9]+]], r[[R1:[0-9]+]]`
ptx: add unconditional and conditional branch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127873 91177308-0d34-0410-b5e6-96231b3b80d8 2011-03-18 11:08:52 +00:00			`%p = icmp ugt i32 %x, %y`
ptx: add analyze/insert/remove branch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128084 91177308-0d34-0410-b5e6-96231b3b80d8 2011-03-22 14:12:00 +00:00			`; CHECK-NEXT: @p0 bra`
			`; CHECK-NOT: bra`
ptx: add unconditional and conditional branch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127873 91177308-0d34-0410-b5e6-96231b3b80d8 2011-03-18 11:08:52 +00:00			`br i1 %p, label %clause.if, label %clause.else`
			`clause.if:`
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8 2011-06-23 18:10:13 +00:00			`; CHECK: mov.u32 r{{[0-9]+}}, r[[R0]]`
ptx: add unconditional and conditional branch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127873 91177308-0d34-0410-b5e6-96231b3b80d8 2011-03-18 11:08:52 +00:00			`ret i32 %x`
			`clause.else:`
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8 2011-06-23 18:10:13 +00:00			`; CHECK: mov.u32 r{{[0-9]+}}, r[[R1]]`
ptx: add unconditional and conditional branch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127873 91177308-0d34-0410-b5e6-96231b3b80d8 2011-03-18 11:08:52 +00:00			`ret i32 %y`
			`}`