2013-03-14 18:27:31 +00:00
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//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsDAGToDAGISel specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEISelDAGToDAG.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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2014-01-07 11:48:04 +00:00
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#include "Mips.h"
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2013-03-14 18:27:31 +00:00
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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2014-03-04 11:45:46 +00:00
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#include "llvm/IR/CFG.h"
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2013-03-14 18:27:31 +00:00
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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2014-04-22 02:41:26 +00:00
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#define DEBUG_TYPE "mips-isel"
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2013-04-09 19:46:01 +00:00
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bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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2014-07-18 23:41:32 +00:00
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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2014-07-10 17:26:51 +00:00
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if (Subtarget->inMips16Mode())
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2013-04-09 19:46:01 +00:00
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return false;
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return MipsDAGToDAGISel::runOnMachineFunction(MF);
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}
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2013-03-14 18:27:31 +00:00
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2013-05-03 18:37:49 +00:00
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void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
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MachineFunction &MF) {
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MachineInstrBuilder MIB(MF, &MI);
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unsigned Mask = MI.getOperand(1).getImm();
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unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
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if (Mask & 1)
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MIB.addReg(Mips::DSPPos, Flag);
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if (Mask & 2)
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MIB.addReg(Mips::DSPSCount, Flag);
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if (Mask & 4)
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MIB.addReg(Mips::DSPCarry, Flag);
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if (Mask & 8)
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MIB.addReg(Mips::DSPOutFlag, Flag);
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if (Mask & 16)
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MIB.addReg(Mips::DSPCCond, Flag);
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if (Mask & 32)
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MIB.addReg(Mips::DSPEFI, Flag);
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}
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2013-08-28 10:26:24 +00:00
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unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
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switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
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default:
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llvm_unreachable("Could not map int to register");
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case 0: return Mips::MSAIR;
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case 1: return Mips::MSACSR;
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case 2: return Mips::MSAAccess;
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case 3: return Mips::MSASave;
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case 4: return Mips::MSAModify;
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case 5: return Mips::MSARequest;
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case 6: return Mips::MSAMap;
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case 7: return Mips::MSAUnmap;
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}
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}
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2013-03-14 18:33:23 +00:00
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bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
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2013-03-14 18:27:31 +00:00
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const MachineInstr& MI) {
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unsigned DstReg = 0, ZeroReg = 0;
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// Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
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if ((MI.getOpcode() == Mips::ADDiu) &&
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(MI.getOperand(1).getReg() == Mips::ZERO) &&
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(MI.getOperand(2).getImm() == 0)) {
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DstReg = MI.getOperand(0).getReg();
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ZeroReg = Mips::ZERO;
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} else if ((MI.getOpcode() == Mips::DADDiu) &&
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(MI.getOperand(1).getReg() == Mips::ZERO_64) &&
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(MI.getOperand(2).getImm() == 0)) {
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DstReg = MI.getOperand(0).getReg();
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ZeroReg = Mips::ZERO_64;
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}
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if (!DstReg)
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return false;
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// Replace uses with ZeroReg.
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for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
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E = MRI->use_end(); U != E;) {
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2014-03-13 23:12:04 +00:00
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MachineOperand &MO = *U;
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2013-03-14 18:27:31 +00:00
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unsigned OpNo = U.getOperandNo();
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MachineInstr *MI = MO.getParent();
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++U;
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// Do not replace if it is a phi's operand or is tied to def operand.
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if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
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continue;
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MO.setReg(ZeroReg);
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}
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return true;
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}
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2013-03-14 18:33:23 +00:00
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void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
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2013-03-14 18:27:31 +00:00
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (!MipsFI->globalBaseRegSet())
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return;
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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2014-08-05 02:39:49 +00:00
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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2013-03-14 18:27:31 +00:00
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
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const TargetRegisterClass *RC;
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2014-11-21 05:58:21 +00:00
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RC = (Subtarget->isABI_N64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
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2013-03-14 18:27:31 +00:00
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V0 = RegInfo.createVirtualRegister(RC);
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V1 = RegInfo.createVirtualRegister(RC);
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2014-07-10 17:26:51 +00:00
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if (Subtarget->isABI_N64()) {
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2013-03-14 18:27:31 +00:00
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MF.getRegInfo().addLiveIn(Mips::T9_64);
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MBB.addLiveIn(Mips::T9_64);
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// daddu $v1, $v0, $t9
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// daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
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.addReg(Mips::T9_64);
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BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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return;
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}
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if (MF.getTarget().getRelocationModel() == Reloc::Static) {
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// Set global register to __gnu_local_gp.
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//
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// lui $v0, %hi(__gnu_local_gp)
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// addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
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return;
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}
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MF.getRegInfo().addLiveIn(Mips::T9);
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MBB.addLiveIn(Mips::T9);
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2014-07-10 17:26:51 +00:00
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if (Subtarget->isABI_N32()) {
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2013-03-14 18:27:31 +00:00
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// addu $v1, $v0, $t9
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// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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return;
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}
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2014-07-10 17:26:51 +00:00
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assert(Subtarget->isABI_O32());
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2013-03-14 18:27:31 +00:00
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// For O32 ABI, the following instruction sequence is emitted to initialize
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// the global base register:
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//
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// 0. lui $2, %hi(_gp_disp)
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// 1. addiu $2, $2, %lo(_gp_disp)
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// 2. addu $globalbasereg, $2, $t9
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//
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// We emit only the last instruction here.
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//
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// GNU linker requires that the first two instructions appear at the beginning
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// of a function and no instructions be inserted before or between them.
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// The two instructions are emitted during lowering to MC layer in order to
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// avoid any reordering.
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//
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// Register $2 (Mips::V0) is added to the list of live-in registers to ensure
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// the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
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// reads it.
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MF.getRegInfo().addLiveIn(Mips::V0);
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MBB.addLiveIn(Mips::V0);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
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.addReg(Mips::V0).addReg(Mips::T9);
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}
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2013-03-14 18:33:23 +00:00
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void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
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initGlobalBaseReg(MF);
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2013-03-14 18:27:31 +00:00
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
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++MFI)
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2013-05-03 18:37:49 +00:00
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for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
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if (I->getOpcode() == Mips::RDDSP)
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addDSPCtrlRegOperands(false, *I, MF);
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else if (I->getOpcode() == Mips::WRDSP)
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addDSPCtrlRegOperands(true, *I, MF);
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else
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replaceUsesWithZeroReg(MRI, *I);
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}
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2013-03-14 18:27:31 +00:00
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}
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2013-03-14 18:39:25 +00:00
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SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
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2013-05-25 02:42:55 +00:00
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SDValue CmpLHS, SDLoc DL,
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2013-03-14 18:39:25 +00:00
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SDNode *Node) const {
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unsigned Opc = InFlag.getOpcode(); (void)Opc;
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assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
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"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
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SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
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SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
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EVT VT = LHS.getValueType();
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2013-04-19 22:22:57 +00:00
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SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
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2013-03-14 18:39:25 +00:00
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SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
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SDValue(Carry, 0), RHS);
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return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
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SDValue(AddCarry, 0));
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}
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2014-03-03 14:31:21 +00:00
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/// Match frameindex
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bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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EVT ValTy = Addr.getValueType();
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Offset = CurDAG->getTargetConstant(0, ValTy);
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return true;
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}
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return false;
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}
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/// Match frameindex+offset and frameindex|offset
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bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
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SDValue &Offset,
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unsigned OffsetBits) const {
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isIntN(OffsetBits, CN->getSExtValue())) {
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EVT ValTy = Addr.getValueType();
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
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return true;
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}
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}
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return false;
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}
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2013-03-14 18:27:31 +00:00
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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// if Address is FI, get the TargetFrameIndex.
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2014-03-03 14:31:21 +00:00
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if (selectAddrFrameIndex(Addr, Base, Offset))
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2013-03-14 18:27:31 +00:00
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return true;
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// on PIC code Load GA
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if (Addr.getOpcode() == MipsISD::Wrapper) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1);
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return true;
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}
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if (TM.getRelocationModel() != Reloc::PIC_) {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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|
|
|
// Addresses of the form FI+const or FI|const
|
2014-03-03 14:31:21 +00:00
|
|
|
if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
|
|
|
|
return true;
|
2013-03-14 18:27:31 +00:00
|
|
|
|
|
|
|
// Operand is a result from an ADD.
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
|
|
// When loading from constant pools, load the lower address part in
|
|
|
|
// the instruction itself. Example, instead of:
|
|
|
|
// lui $2, %hi($CPI1_0)
|
|
|
|
// addiu $2, $2, %lo($CPI1_0)
|
|
|
|
// lwc1 $f0, 0($2)
|
|
|
|
// Generate:
|
|
|
|
// lui $2, %hi($CPI1_0)
|
|
|
|
// lwc1 $f0, %lo($CPI1_0)($2)
|
|
|
|
if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
|
|
|
|
Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
|
|
|
|
SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
|
|
|
|
if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
|
|
|
|
isa<JumpTableSDNode>(Opnd0)) {
|
|
|
|
Base = Addr.getOperand(0);
|
|
|
|
Offset = Opnd0;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-08-28 12:04:29 +00:00
|
|
|
/// ComplexPattern used on MipsInstrInfo
|
|
|
|
/// Used on Mips Load/Store instructions
|
|
|
|
bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
|
|
|
// Operand is a result from an ADD.
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
|
|
Base = Addr.getOperand(0);
|
|
|
|
Offset = Addr.getOperand(1);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-03-14 18:27:31 +00:00
|
|
|
bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
|
|
|
Base = Addr;
|
|
|
|
Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
|
|
|
return selectAddrRegImm(Addr, Base, Offset) ||
|
|
|
|
selectAddrDefault(Addr, Base, Offset);
|
|
|
|
}
|
|
|
|
|
2014-03-03 14:31:21 +00:00
|
|
|
bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
|
2013-08-13 20:19:16 +00:00
|
|
|
SDValue &Offset) const {
|
2014-03-03 14:31:21 +00:00
|
|
|
if (selectAddrFrameIndex(Addr, Base, Offset))
|
|
|
|
return true;
|
2013-08-13 20:19:16 +00:00
|
|
|
|
2014-03-03 14:31:21 +00:00
|
|
|
if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
|
|
|
|
return true;
|
2013-08-13 20:19:16 +00:00
|
|
|
|
2014-03-03 14:31:21 +00:00
|
|
|
return false;
|
|
|
|
}
|
2013-08-13 20:19:16 +00:00
|
|
|
|
2014-03-03 14:31:21 +00:00
|
|
|
/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
|
|
|
|
bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
|
|
|
if (selectAddrFrameIndex(Addr, Base, Offset))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
|
|
|
|
return true;
|
2013-08-13 20:19:16 +00:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
|
|
|
return selectAddrRegImm12(Addr, Base, Offset) ||
|
|
|
|
selectAddrDefault(Addr, Base, Offset);
|
|
|
|
}
|
|
|
|
|
2014-03-03 14:31:21 +00:00
|
|
|
bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
|
|
|
|
SDValue &Offset) const {
|
|
|
|
if (selectAddrRegImm10(Addr, Base, Offset))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (selectAddrDefault(Addr, Base, Offset))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-09-24 13:33:07 +00:00
|
|
|
// Select constant vector splats.
|
|
|
|
//
|
|
|
|
// Returns true and sets Imm if:
|
|
|
|
// * MSA is enabled
|
|
|
|
// * N is a ISD::BUILD_VECTOR representing a constant splat
|
|
|
|
bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
|
2014-07-10 17:26:51 +00:00
|
|
|
if (!Subtarget->hasMSA())
|
2013-09-24 13:33:07 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
|
|
|
|
|
2014-04-25 05:30:21 +00:00
|
|
|
if (!Node)
|
2013-09-24 13:33:07 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
APInt SplatValue, SplatUndef;
|
|
|
|
unsigned SplatBitSize;
|
|
|
|
bool HasAnyUndefs;
|
|
|
|
|
|
|
|
if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
|
|
|
|
HasAnyUndefs, 8,
|
2014-07-10 17:26:51 +00:00
|
|
|
!Subtarget->isLittle()))
|
2013-09-24 13:33:07 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
Imm = SplatValue;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats.
|
|
|
|
//
|
|
|
|
// In addition to the requirements of selectVSplat(), this function returns
|
|
|
|
// true and sets Imm if:
|
|
|
|
// * The splat value is the same width as the elements of the vector
|
|
|
|
// * The splat value fits in an integer with the specified signed-ness and
|
|
|
|
// width.
|
|
|
|
//
|
|
|
|
// This function looks through ISD::BITCAST nodes.
|
|
|
|
// TODO: This might not be appropriate for big-endian MSA since BITCAST is
|
|
|
|
// sometimes a shuffle in big-endian mode.
|
|
|
|
//
|
|
|
|
// It's worth noting that this function is not used as part of the selection
|
|
|
|
// of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
|
|
|
|
// instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
|
|
|
|
// MipsSEDAGToDAGISel::selectNode.
|
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
|
|
|
|
unsigned ImmBitSize) const {
|
|
|
|
APInt ImmValue;
|
|
|
|
EVT EltTy = N->getValueType(0).getVectorElementType();
|
|
|
|
|
|
|
|
if (N->getOpcode() == ISD::BITCAST)
|
|
|
|
N = N->getOperand(0);
|
|
|
|
|
|
|
|
if (selectVSplat (N.getNode(), ImmValue) &&
|
|
|
|
ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
|
|
|
|
if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
|
|
|
|
(!Signed && ImmValue.isIntN(ImmBitSize))) {
|
|
|
|
Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats.
|
2013-09-27 11:48:57 +00:00
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatUimm1(SDValue N, SDValue &Imm) const {
|
|
|
|
return selectVSplatCommon(N, Imm, false, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatUimm2(SDValue N, SDValue &Imm) const {
|
|
|
|
return selectVSplatCommon(N, Imm, false, 2);
|
|
|
|
}
|
|
|
|
|
2013-09-24 13:33:07 +00:00
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatUimm3(SDValue N, SDValue &Imm) const {
|
|
|
|
return selectVSplatCommon(N, Imm, false, 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats.
|
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatUimm4(SDValue N, SDValue &Imm) const {
|
|
|
|
return selectVSplatCommon(N, Imm, false, 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats.
|
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatUimm5(SDValue N, SDValue &Imm) const {
|
|
|
|
return selectVSplatCommon(N, Imm, false, 5);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats.
|
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatUimm6(SDValue N, SDValue &Imm) const {
|
|
|
|
return selectVSplatCommon(N, Imm, false, 6);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats.
|
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatUimm8(SDValue N, SDValue &Imm) const {
|
|
|
|
return selectVSplatCommon(N, Imm, false, 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats.
|
|
|
|
bool MipsSEDAGToDAGISel::
|
|
|
|
selectVSplatSimm5(SDValue N, SDValue &Imm) const {
|
|
|
|
return selectVSplatCommon(N, Imm, true, 5);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats whose value is a power of 2.
|
|
|
|
//
|
|
|
|
// In addition to the requirements of selectVSplat(), this function returns
|
|
|
|
// true and sets Imm if:
|
|
|
|
// * The splat value is the same width as the elements of the vector
|
|
|
|
// * The splat value is a power of two.
|
|
|
|
//
|
|
|
|
// This function looks through ISD::BITCAST nodes.
|
|
|
|
// TODO: This might not be appropriate for big-endian MSA since BITCAST is
|
|
|
|
// sometimes a shuffle in big-endian mode.
|
|
|
|
bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
|
|
|
|
APInt ImmValue;
|
|
|
|
EVT EltTy = N->getValueType(0).getVectorElementType();
|
|
|
|
|
|
|
|
if (N->getOpcode() == ISD::BITCAST)
|
|
|
|
N = N->getOperand(0);
|
|
|
|
|
|
|
|
if (selectVSplat (N.getNode(), ImmValue) &&
|
|
|
|
ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
|
|
|
|
int32_t Log2 = ImmValue.exactLogBase2();
|
|
|
|
|
|
|
|
if (Log2 != -1) {
|
|
|
|
Imm = CurDAG->getTargetConstant(Log2, EltTy);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-10-30 14:45:14 +00:00
|
|
|
// Select constant vector splats whose value only has a consecutive sequence
|
|
|
|
// of left-most bits set (e.g. 0b11...1100...00).
|
|
|
|
//
|
|
|
|
// In addition to the requirements of selectVSplat(), this function returns
|
|
|
|
// true and sets Imm if:
|
|
|
|
// * The splat value is the same width as the elements of the vector
|
|
|
|
// * The splat value is a consecutive sequence of left-most bits.
|
|
|
|
//
|
|
|
|
// This function looks through ISD::BITCAST nodes.
|
|
|
|
// TODO: This might not be appropriate for big-endian MSA since BITCAST is
|
|
|
|
// sometimes a shuffle in big-endian mode.
|
|
|
|
bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
|
|
|
|
APInt ImmValue;
|
|
|
|
EVT EltTy = N->getValueType(0).getVectorElementType();
|
|
|
|
|
|
|
|
if (N->getOpcode() == ISD::BITCAST)
|
|
|
|
N = N->getOperand(0);
|
|
|
|
|
|
|
|
if (selectVSplat(N.getNode(), ImmValue) &&
|
|
|
|
ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
|
|
|
|
// Extract the run of set bits starting with bit zero from the bitwise
|
|
|
|
// inverse of ImmValue, and test that the inverse of this is the same
|
|
|
|
// as the original value.
|
|
|
|
if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
|
|
|
|
|
|
|
|
Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Select constant vector splats whose value only has a consecutive sequence
|
|
|
|
// of right-most bits set (e.g. 0b00...0011...11).
|
|
|
|
//
|
|
|
|
// In addition to the requirements of selectVSplat(), this function returns
|
|
|
|
// true and sets Imm if:
|
|
|
|
// * The splat value is the same width as the elements of the vector
|
|
|
|
// * The splat value is a consecutive sequence of right-most bits.
|
|
|
|
//
|
|
|
|
// This function looks through ISD::BITCAST nodes.
|
|
|
|
// TODO: This might not be appropriate for big-endian MSA since BITCAST is
|
|
|
|
// sometimes a shuffle in big-endian mode.
|
|
|
|
bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
|
|
|
|
APInt ImmValue;
|
|
|
|
EVT EltTy = N->getValueType(0).getVectorElementType();
|
|
|
|
|
|
|
|
if (N->getOpcode() == ISD::BITCAST)
|
|
|
|
N = N->getOperand(0);
|
|
|
|
|
|
|
|
if (selectVSplat(N.getNode(), ImmValue) &&
|
|
|
|
ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
|
|
|
|
// Extract the run of set bits starting with bit zero, and test that the
|
|
|
|
// result is the same as the original value
|
|
|
|
if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
|
|
|
|
Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-11-12 10:45:18 +00:00
|
|
|
bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
|
|
|
|
SDValue &Imm) const {
|
|
|
|
APInt ImmValue;
|
|
|
|
EVT EltTy = N->getValueType(0).getVectorElementType();
|
|
|
|
|
|
|
|
if (N->getOpcode() == ISD::BITCAST)
|
|
|
|
N = N->getOperand(0);
|
|
|
|
|
|
|
|
if (selectVSplat(N.getNode(), ImmValue) &&
|
|
|
|
ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
|
|
|
|
int32_t Log2 = (~ImmValue).exactLogBase2();
|
|
|
|
|
|
|
|
if (Log2 != -1) {
|
|
|
|
Imm = CurDAG->getTargetConstant(Log2, EltTy);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-03-14 18:33:23 +00:00
|
|
|
std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
|
2013-03-14 18:27:31 +00:00
|
|
|
unsigned Opcode = Node->getOpcode();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Node);
|
2013-03-14 18:27:31 +00:00
|
|
|
|
|
|
|
///
|
|
|
|
// Instruction Selection not handled by the auto-generated
|
|
|
|
// tablegen selection should be handled here.
|
|
|
|
///
|
|
|
|
SDNode *Result;
|
|
|
|
|
|
|
|
switch(Opcode) {
|
|
|
|
default: break;
|
|
|
|
|
2013-03-14 18:39:25 +00:00
|
|
|
case ISD::SUBE: {
|
|
|
|
SDValue InFlag = Node->getOperand(2);
|
|
|
|
Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
|
|
|
|
return std::make_pair(true, Result);
|
|
|
|
}
|
2013-03-14 18:27:31 +00:00
|
|
|
|
2013-03-14 18:39:25 +00:00
|
|
|
case ISD::ADDE: {
|
2014-07-10 17:26:51 +00:00
|
|
|
if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
|
2013-04-13 00:55:41 +00:00
|
|
|
break;
|
2013-03-14 18:39:25 +00:00
|
|
|
SDValue InFlag = Node->getOperand(2);
|
|
|
|
Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
|
2013-03-14 18:27:31 +00:00
|
|
|
return std::make_pair(true, Result);
|
|
|
|
}
|
|
|
|
|
|
|
|
case ISD::ConstantFP: {
|
|
|
|
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
|
|
|
|
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
|
2014-07-10 17:26:51 +00:00
|
|
|
if (Subtarget->isGP64bit()) {
|
2013-03-14 18:33:23 +00:00
|
|
|
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
|
2013-03-14 18:27:31 +00:00
|
|
|
Mips::ZERO_64, MVT::i64);
|
2013-03-14 18:33:23 +00:00
|
|
|
Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
|
2014-07-10 17:26:51 +00:00
|
|
|
} else if (Subtarget->isFP64bit()) {
|
2013-11-18 13:12:43 +00:00
|
|
|
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
|
|
|
|
Mips::ZERO, MVT::i32);
|
|
|
|
Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
|
|
|
|
Zero, Zero);
|
2013-03-14 18:27:31 +00:00
|
|
|
} else {
|
2013-03-14 18:33:23 +00:00
|
|
|
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
|
2013-03-14 18:27:31 +00:00
|
|
|
Mips::ZERO, MVT::i32);
|
2013-03-14 18:33:23 +00:00
|
|
|
Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
|
2013-03-14 18:27:31 +00:00
|
|
|
Zero);
|
|
|
|
}
|
|
|
|
|
|
|
|
return std::make_pair(true, Result);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case ISD::Constant: {
|
|
|
|
const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
|
|
|
|
unsigned Size = CN->getValueSizeInBits(0);
|
|
|
|
|
|
|
|
if (Size == 32)
|
|
|
|
break;
|
|
|
|
|
|
|
|
MipsAnalyzeImmediate AnalyzeImm;
|
|
|
|
int64_t Imm = CN->getSExtValue();
|
|
|
|
|
|
|
|
const MipsAnalyzeImmediate::InstSeq &Seq =
|
|
|
|
AnalyzeImm.Analyze(Imm, Size, false);
|
|
|
|
|
|
|
|
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(CN);
|
2013-03-14 18:27:31 +00:00
|
|
|
SDNode *RegOpnd;
|
|
|
|
SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
|
|
|
|
MVT::i64);
|
|
|
|
|
|
|
|
// The first instruction can be a LUi which is different from other
|
|
|
|
// instructions (ADDiu, ORI and SLL) in that it does not have a register
|
|
|
|
// operand.
|
|
|
|
if (Inst->Opc == Mips::LUi64)
|
|
|
|
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
|
|
|
|
else
|
|
|
|
RegOpnd =
|
|
|
|
CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
|
|
|
|
CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
|
|
|
|
ImmOpnd);
|
|
|
|
|
|
|
|
// The remaining instructions in the sequence are handled here.
|
|
|
|
for (++Inst; Inst != Seq.end(); ++Inst) {
|
|
|
|
ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
|
|
|
|
MVT::i64);
|
|
|
|
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
|
|
|
|
SDValue(RegOpnd, 0), ImmOpnd);
|
|
|
|
}
|
|
|
|
|
|
|
|
return std::make_pair(true, RegOpnd);
|
|
|
|
}
|
|
|
|
|
2013-08-28 10:26:24 +00:00
|
|
|
case ISD::INTRINSIC_W_CHAIN: {
|
|
|
|
switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case Intrinsic::mips_cfcmsa: {
|
|
|
|
SDValue ChainIn = Node->getOperand(0);
|
|
|
|
SDValue RegIdx = Node->getOperand(2);
|
|
|
|
SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
|
|
|
|
getMSACtrlReg(RegIdx), MVT::i32);
|
|
|
|
return std::make_pair(true, Reg.getNode());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-08-28 10:44:47 +00:00
|
|
|
case ISD::INTRINSIC_WO_CHAIN: {
|
|
|
|
switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case Intrinsic::mips_move_v:
|
|
|
|
// Like an assignment but will always produce a move.v even if
|
|
|
|
// unnecessary.
|
|
|
|
return std::make_pair(true,
|
|
|
|
CurDAG->getMachineNode(Mips::MOVE_V, DL,
|
|
|
|
Node->getValueType(0),
|
|
|
|
Node->getOperand(1)));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-08-28 10:26:24 +00:00
|
|
|
case ISD::INTRINSIC_VOID: {
|
|
|
|
switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case Intrinsic::mips_ctcmsa: {
|
|
|
|
SDValue ChainIn = Node->getOperand(0);
|
|
|
|
SDValue RegIdx = Node->getOperand(2);
|
|
|
|
SDValue Value = Node->getOperand(3);
|
|
|
|
SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
|
|
|
|
getMSACtrlReg(RegIdx), Value);
|
|
|
|
return std::make_pair(true, ChainOut.getNode());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-03-14 18:27:31 +00:00
|
|
|
case MipsISD::ThreadPointer: {
|
2013-06-19 21:36:55 +00:00
|
|
|
EVT PtrVT = getTargetLowering()->getPointerTy();
|
2013-08-08 21:37:32 +00:00
|
|
|
unsigned RdhwrOpc, DestReg;
|
2013-03-14 18:27:31 +00:00
|
|
|
|
|
|
|
if (PtrVT == MVT::i32) {
|
|
|
|
RdhwrOpc = Mips::RDHWR;
|
|
|
|
DestReg = Mips::V1;
|
|
|
|
} else {
|
|
|
|
RdhwrOpc = Mips::RDHWR64;
|
|
|
|
DestReg = Mips::V1_64;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDNode *Rdhwr =
|
2013-05-25 02:42:55 +00:00
|
|
|
CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
|
2013-03-14 18:27:31 +00:00
|
|
|
Node->getValueType(0),
|
2013-08-08 21:37:32 +00:00
|
|
|
CurDAG->getRegister(Mips::HWR29, MVT::i32));
|
2013-03-14 18:33:23 +00:00
|
|
|
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
|
2013-03-14 18:27:31 +00:00
|
|
|
SDValue(Rdhwr, 0));
|
2013-03-14 18:33:23 +00:00
|
|
|
SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
|
2013-03-14 18:27:31 +00:00
|
|
|
ReplaceUses(SDValue(Node, 0), ResNode);
|
|
|
|
return std::make_pair(true, ResNode.getNode());
|
|
|
|
}
|
2013-03-30 01:36:35 +00:00
|
|
|
|
2013-09-24 13:33:07 +00:00
|
|
|
case ISD::BUILD_VECTOR: {
|
|
|
|
// Select appropriate ldi.[bhwd] instructions for constant splats of
|
|
|
|
// 128-bit when MSA is enabled. Fixup any register class mismatches that
|
|
|
|
// occur as a result.
|
|
|
|
//
|
|
|
|
// This allows the compiler to use a wider range of immediates than would
|
|
|
|
// otherwise be allowed. If, for example, v4i32 could only use ldi.h then
|
|
|
|
// it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
|
|
|
|
// 0x01010101 } without using a constant pool. This would be sub-optimal
|
|
|
|
// when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
|
|
|
|
// same set/ of registers. Similarly, ldi.h isn't capable of producing {
|
|
|
|
// 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
|
|
|
|
|
|
|
|
BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
|
|
|
|
APInt SplatValue, SplatUndef;
|
|
|
|
unsigned SplatBitSize;
|
|
|
|
bool HasAnyUndefs;
|
|
|
|
unsigned LdiOp;
|
|
|
|
EVT ResVecTy = BVN->getValueType(0);
|
|
|
|
EVT ViaVecTy;
|
|
|
|
|
2014-07-10 17:26:51 +00:00
|
|
|
if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
|
2014-04-25 05:30:21 +00:00
|
|
|
return std::make_pair(false, nullptr);
|
2013-09-24 13:33:07 +00:00
|
|
|
|
|
|
|
if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
|
|
|
|
HasAnyUndefs, 8,
|
2014-07-10 17:26:51 +00:00
|
|
|
!Subtarget->isLittle()))
|
2014-04-25 05:30:21 +00:00
|
|
|
return std::make_pair(false, nullptr);
|
2013-09-24 13:33:07 +00:00
|
|
|
|
|
|
|
switch (SplatBitSize) {
|
|
|
|
default:
|
2014-04-25 05:30:21 +00:00
|
|
|
return std::make_pair(false, nullptr);
|
2013-09-24 13:33:07 +00:00
|
|
|
case 8:
|
|
|
|
LdiOp = Mips::LDI_B;
|
|
|
|
ViaVecTy = MVT::v16i8;
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
LdiOp = Mips::LDI_H;
|
|
|
|
ViaVecTy = MVT::v8i16;
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
LdiOp = Mips::LDI_W;
|
|
|
|
ViaVecTy = MVT::v4i32;
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
LdiOp = Mips::LDI_D;
|
|
|
|
ViaVecTy = MVT::v2i64;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!SplatValue.isSignedIntN(10))
|
2014-04-25 05:30:21 +00:00
|
|
|
return std::make_pair(false, nullptr);
|
2013-09-24 13:33:07 +00:00
|
|
|
|
|
|
|
SDValue Imm = CurDAG->getTargetConstant(SplatValue,
|
|
|
|
ViaVecTy.getVectorElementType());
|
|
|
|
|
|
|
|
SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
|
|
|
|
|
|
|
|
if (ResVecTy != ViaVecTy) {
|
|
|
|
// If LdiOp is writing to a different register class to ResVecTy, then
|
|
|
|
// fix it up here. This COPY_TO_REGCLASS should never cause a move.v
|
|
|
|
// since the source and destination register sets contain the same
|
|
|
|
// registers.
|
|
|
|
const TargetLowering *TLI = getTargetLowering();
|
|
|
|
MVT ResVecTySimple = ResVecTy.getSimpleVT();
|
|
|
|
const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
|
|
|
|
Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
|
|
|
|
ResVecTy, SDValue(Res, 0),
|
|
|
|
CurDAG->getTargetConstant(RC->getID(),
|
|
|
|
MVT::i32));
|
|
|
|
}
|
|
|
|
|
|
|
|
return std::make_pair(true, Res);
|
|
|
|
}
|
|
|
|
|
2013-03-14 18:27:31 +00:00
|
|
|
}
|
|
|
|
|
2014-04-25 05:30:21 +00:00
|
|
|
return std::make_pair(false, nullptr);
|
2013-03-14 18:27:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
|
|
|
|
return new MipsSEDAGToDAGISel(TM);
|
|
|
|
}
|