6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-09 10:05:41 +00:00
Code Issues Projects Releases Wiki Activity
f801675207
llvm-6502/test/CodeGen/Mips/eh.ll

68 lines
2.2 KiB
LLVM
Raw Normal View History

Fix test cases. Generate code for Mips32r1 unless a Mips32r2 feature is tested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:14:58 +00:00
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB
Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: - cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 02:17:21 +00:00
@g1 = global double 0.000000e+00, align 8
@_ZTId = external constant i8*
define void @_Z1fd(double %i2) {
entry:
; CHECK-EL: addiu $sp, $sp
; CHECK-EL: .cfi_def_cfa_offset
; CHECK-EL: sdc1 $f20
; CHECK-EL: sw $ra
; CHECK-EL: .cfi_offset 52, -8
; CHECK-EL: .cfi_offset 53, -4
; CHECK-EB: .cfi_offset 53, -8
; CHECK-EB: .cfi_offset 52, -4
; CHECK-EL: .cfi_offset 31, -12
%exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind
%0 = bitcast i8* %exception to double*
store double 3.200000e+00, double* %0, align 8, !tbaa !0
invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTId to i8*), i8* null) noreturn
to label %unreachable unwind label %lpad
lpad: ; preds = %entry
; CHECK-EL: # %lpad
Flip the new block-placement pass to be on by default. This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 13:49:17 +00:00
; CHECK-EL: bne $5
Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: - cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 02:17:21 +00:00
Better fix for this testcase. Update it to the new EH scheme entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 21:27:08 +00:00
%exn.val = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
catch i8* bitcast (i8** @_ZTId to i8*)
%exn = extractvalue { i8*, i32 } %exn.val, 0
%sel = extractvalue { i8*, i32 } %exn.val, 1
Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: - cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 02:17:21 +00:00
%1 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTId to i8*)) nounwind
Better fix for this testcase. Update it to the new EH scheme entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 21:27:08 +00:00
%2 = icmp eq i32 %sel, %1
Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: - cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 02:17:21 +00:00
br i1 %2, label %catch, label %eh.resume
catch: ; preds = %lpad
%3 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind
%4 = bitcast i8* %3 to double*
%exn.scalar = load double* %4, align 8
%add = fadd double %exn.scalar, %i2
store double %add, double* @g1, align 8, !tbaa !0
tail call void @__cxa_end_catch() nounwind
ret void
eh.resume: ; preds = %lpad
Better fix for this testcase. Update it to the new EH scheme entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 21:27:08 +00:00
resume { i8*, i32 } %exn.val
Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: - cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 02:17:21 +00:00
unreachable: ; preds = %entry
unreachable
}
declare i8* @__cxa_allocate_exception(i32)
declare i32 @__gxx_personality_v0(...)
declare i32 @llvm.eh.typeid.for(i8*) nounwind
declare void @__cxa_throw(i8*, i8*, i8*)
declare i8* @__cxa_begin_catch(i8*)
declare void @__cxa_end_catch()
!0 = metadata !{metadata !"double", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
Reference in New Issue Copy Permalink