2007-07-11 22:44:21 +00:00
|
|
|
//===-- MipsMachineFunctionInfo.h - Private data used for Mips ----*- C++ -*-=//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-07-11 22:44:21 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file declares the Mips specific subclass of MachineFunctionInfo.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef MIPS_MACHINE_FUNCTION_INFO_H
|
|
|
|
#define MIPS_MACHINE_FUNCTION_INFO_H
|
|
|
|
|
2009-01-05 17:59:02 +00:00
|
|
|
#include "llvm/ADT/SmallVector.h"
|
2007-08-28 05:04:41 +00:00
|
|
|
#include "llvm/ADT/VectorExtras.h"
|
2007-07-11 22:44:21 +00:00
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
2007-08-28 05:04:41 +00:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
2007-07-11 22:44:21 +00:00
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
|
|
|
|
/// MipsFunctionInfo - This class is derived from MachineFunction private
|
|
|
|
/// Mips target-specific information for each MachineFunction.
|
|
|
|
class MipsFunctionInfo : public MachineFunctionInfo {
|
|
|
|
|
|
|
|
private:
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// Holds for each function where on the stack the Frame Pointer must be
|
2008-08-06 06:14:43 +00:00
|
|
|
/// saved. This is used on Prologue and Epilogue to emit FP save/restore
|
2007-07-11 22:44:21 +00:00
|
|
|
int FPStackOffset;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// Holds for each function where on the stack the Return Address must be
|
2008-08-06 06:14:43 +00:00
|
|
|
/// saved. This is used on Prologue and Epilogue to emit RA save/restore
|
2007-07-11 22:44:21 +00:00
|
|
|
int RAStackOffset;
|
|
|
|
|
2008-08-06 06:14:43 +00:00
|
|
|
/// At each function entry, two special bitmask directives must be emitted
|
|
|
|
/// to help debugging, for CPU and FPU callee saved registers. Both need
|
|
|
|
/// the negative offset from the final stack size and its higher registers
|
|
|
|
/// location on the stack.
|
|
|
|
int CPUTopSavedRegOff;
|
|
|
|
int FPUTopSavedRegOff;
|
|
|
|
|
2007-08-28 05:04:41 +00:00
|
|
|
/// MipsFIHolder - Holds a FrameIndex and it's Stack Pointer Offset
|
|
|
|
struct MipsFIHolder {
|
|
|
|
|
|
|
|
int FI;
|
|
|
|
int SPOffset;
|
|
|
|
|
|
|
|
MipsFIHolder(int FrameIndex, int StackPointerOffset)
|
|
|
|
: FI(FrameIndex), SPOffset(StackPointerOffset) {}
|
|
|
|
};
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// When PIC is used the GP must be saved on the stack on the function
|
|
|
|
/// prologue and must be reloaded from this stack location after every
|
|
|
|
/// call. A reference to its stack location and frame index must be kept
|
|
|
|
/// to be used on emitPrologue and processFunctionBeforeFrameFinalized.
|
2007-11-05 03:02:32 +00:00
|
|
|
MipsFIHolder GPHolder;
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
/// On LowerFormalArguments the stack size is unknown, so the Stack
|
2008-08-06 06:14:43 +00:00
|
|
|
/// Pointer Offset calculation of "not in register arguments" must be
|
|
|
|
/// postponed to emitPrologue.
|
2007-08-28 05:04:41 +00:00
|
|
|
SmallVector<MipsFIHolder, 16> FnLoadArgs;
|
|
|
|
bool HasLoadArgs;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// When VarArgs, we must write registers back to caller stack, preserving
|
|
|
|
// on register arguments. Since the stack size is unknown on
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
// LowerFormalArguments, the Stack Pointer Offset calculation must be
|
2007-08-28 05:04:41 +00:00
|
|
|
// postponed to emitPrologue.
|
|
|
|
SmallVector<MipsFIHolder, 4> FnStoreVarArgs;
|
|
|
|
bool HasStoreVarArgs;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
/// SRetReturnReg - Some subtargets require that sret lowering includes
|
|
|
|
/// returning the value of the returned struct in a register. This field
|
|
|
|
/// holds the virtual register into which the sret argument is passed.
|
|
|
|
unsigned SRetReturnReg;
|
|
|
|
|
2009-06-03 20:30:14 +00:00
|
|
|
/// GlobalBaseReg - keeps track of the virtual register initialized for
|
|
|
|
/// use as the global base register. This is used for PIC in some PIC
|
|
|
|
/// relocation models.
|
|
|
|
unsigned GlobalBaseReg;
|
|
|
|
|
2007-07-11 22:44:21 +00:00
|
|
|
public:
|
|
|
|
MipsFunctionInfo(MachineFunction& MF)
|
2008-08-06 06:14:43 +00:00
|
|
|
: FPStackOffset(0), RAStackOffset(0), CPUTopSavedRegOff(0),
|
|
|
|
FPUTopSavedRegOff(0), GPHolder(-1,-1), HasLoadArgs(false),
|
2009-06-03 20:30:14 +00:00
|
|
|
HasStoreVarArgs(false), SRetReturnReg(0), GlobalBaseReg(0)
|
2007-07-11 22:44:21 +00:00
|
|
|
{}
|
|
|
|
|
|
|
|
int getFPStackOffset() const { return FPStackOffset; }
|
|
|
|
void setFPStackOffset(int Off) { FPStackOffset = Off; }
|
|
|
|
|
|
|
|
int getRAStackOffset() const { return RAStackOffset; }
|
|
|
|
void setRAStackOffset(int Off) { RAStackOffset = Off; }
|
|
|
|
|
2008-08-06 06:14:43 +00:00
|
|
|
int getCPUTopSavedRegOff() const { return CPUTopSavedRegOff; }
|
|
|
|
void setCPUTopSavedRegOff(int Off) { CPUTopSavedRegOff = Off; }
|
|
|
|
|
|
|
|
int getFPUTopSavedRegOff() const { return FPUTopSavedRegOff; }
|
|
|
|
void setFPUTopSavedRegOff(int Off) { FPUTopSavedRegOff = Off; }
|
|
|
|
|
2007-11-05 03:02:32 +00:00
|
|
|
int getGPStackOffset() const { return GPHolder.SPOffset; }
|
|
|
|
int getGPFI() const { return GPHolder.FI; }
|
|
|
|
void setGPStackOffset(int Off) { GPHolder.SPOffset = Off; }
|
|
|
|
void setGPFI(int FI) { GPHolder.FI = FI; }
|
2009-11-09 14:27:49 +00:00
|
|
|
bool needGPSaveRestore() const { return GPHolder.SPOffset != -1; }
|
2007-10-09 03:01:19 +00:00
|
|
|
|
2007-08-28 05:04:41 +00:00
|
|
|
bool hasLoadArgs() const { return HasLoadArgs; }
|
|
|
|
bool hasStoreVarArgs() const { return HasStoreVarArgs; }
|
|
|
|
|
|
|
|
void recordLoadArgsFI(int FI, int SPOffset) {
|
|
|
|
if (!HasLoadArgs) HasLoadArgs=true;
|
|
|
|
FnLoadArgs.push_back(MipsFIHolder(FI, SPOffset));
|
|
|
|
}
|
|
|
|
void recordStoreVarArgsFI(int FI, int SPOffset) {
|
|
|
|
if (!HasStoreVarArgs) HasStoreVarArgs=true;
|
|
|
|
FnStoreVarArgs.push_back(MipsFIHolder(FI, SPOffset));
|
|
|
|
}
|
|
|
|
|
|
|
|
void adjustLoadArgsFI(MachineFrameInfo *MFI) const {
|
|
|
|
if (!hasLoadArgs()) return;
|
|
|
|
for (unsigned i = 0, e = FnLoadArgs.size(); i != e; ++i)
|
|
|
|
MFI->setObjectOffset( FnLoadArgs[i].FI, FnLoadArgs[i].SPOffset );
|
|
|
|
}
|
|
|
|
void adjustStoreVarArgsFI(MachineFrameInfo *MFI) const {
|
|
|
|
if (!hasStoreVarArgs()) return;
|
|
|
|
for (unsigned i = 0, e = FnStoreVarArgs.size(); i != e; ++i)
|
|
|
|
MFI->setObjectOffset( FnStoreVarArgs[i].FI, FnStoreVarArgs[i].SPOffset );
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
unsigned getSRetReturnReg() const { return SRetReturnReg; }
|
|
|
|
void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
|
2009-06-03 20:30:14 +00:00
|
|
|
|
|
|
|
unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
|
|
|
|
void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
|
2007-07-11 22:44:21 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end of namespace llvm
|
|
|
|
|
2007-08-28 05:04:41 +00:00
|
|
|
#endif // MIPS_MACHINE_FUNCTION_INFO_H
|