mirror of
https://github.com/c64scene-ar/llvm-6502.git
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107 lines
4.1 KiB
TableGen
107 lines
4.1 KiB
TableGen
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//===-- Mos6502.td - Describe the Mos6502 Target Machine -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// MOS6502 Subtarget features.
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//
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def FeatureV9
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: SubtargetFeature<"v9", "IsV9", "true",
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"Enable MOS6502-V9 instructions">;
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def FeatureV8Deprecated
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: SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
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"Enable deprecated V8 instructions in V9 mode">;
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def FeatureVIS
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: SubtargetFeature<"vis", "IsVIS", "true",
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"Enable UltraMOS6502 Visual Instruction Set extensions">;
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def FeatureVIS2
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: SubtargetFeature<"vis2", "IsVIS2", "true",
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"Enable Visual Instruction Set extensions II">;
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def FeatureVIS3
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: SubtargetFeature<"vis3", "IsVIS3", "true",
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"Enable Visual Instruction Set extensions III">;
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def FeatureHardQuad
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: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
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"Enable quad-word floating point instructions">;
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def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
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"Use the popc (population count) instruction">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "Mos6502RegisterInfo.td"
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include "Mos6502CallingConv.td"
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include "Mos6502InstrInfo.td"
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def Mos6502InstrInfo : InstrInfo;
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def Mos6502AsmParser : AsmParser {
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bit ShouldEmitMatchRegisterName = 0;
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}
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//===----------------------------------------------------------------------===//
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// MOS6502 processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"v7", []>;
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def : Proc<"v8", []>;
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def : Proc<"supermos6502", []>;
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def : Proc<"mos6502lite", []>;
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def : Proc<"f934", []>;
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def : Proc<"hypermos6502", []>;
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def : Proc<"mos6502lite86x", []>;
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def : Proc<"mos6502let", []>;
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def : Proc<"tsc701", []>;
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def : Proc<"v9", [FeatureV9]>;
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def : Proc<"ultramos6502", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
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def : Proc<"ultramos65023", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
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FeatureVIS2]>;
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def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
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FeatureVIS2]>;
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def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2]>;
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def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2]>;
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def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2, FeatureVIS3]>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def Mos6502AsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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}
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def Mos6502 : Target {
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// Pull in Instruction Info:
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let InstructionSet = Mos6502InstrInfo;
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let AssemblyParsers = [Mos6502AsmParser];
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let AssemblyWriters = [Mos6502AsmWriter];
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}
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