llvm-6502/test/CodeGen/X86/exedepsfix-broadcast.ll

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; RUN: llc -O3 -mtriple=x86_64-apple-macosx -o - < %s -mattr=+avx2 -enable-unsafe-fp-math -mcpu=core2 | FileCheck %s
; Check that the ExeDepsFix pass correctly fixes the domain for broadcast instructions.
; <rdar://problem/16354675>
; CHECK-LABEL: ExeDepsFix_broadcastss
; CHECK: broadcastss
; CHECK: vandps
; CHECK: vmaxps
; CHECK: ret
define <4 x float> @ExeDepsFix_broadcastss(<4 x float> %arg, <4 x float> %arg2) {
%bitcast = bitcast <4 x float> %arg to <4 x i32>
%and = and <4 x i32> %bitcast, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
%floatcast = bitcast <4 x i32> %and to <4 x float>
%max_is_x = fcmp oge <4 x float> %floatcast, %arg2
%max = select <4 x i1> %max_is_x, <4 x float> %floatcast, <4 x float> %arg2
ret <4 x float> %max
}
; CHECK-LABEL: ExeDepsFix_broadcastss256
; CHECK: broadcastss
; CHECK: vandps
; CHECK: vmaxps
; CHECK: ret
define <8 x float> @ExeDepsFix_broadcastss256(<8 x float> %arg, <8 x float> %arg2) {
%bitcast = bitcast <8 x float> %arg to <8 x i32>
%and = and <8 x i32> %bitcast, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
%floatcast = bitcast <8 x i32> %and to <8 x float>
%max_is_x = fcmp oge <8 x float> %floatcast, %arg2
%max = select <8 x i1> %max_is_x, <8 x float> %floatcast, <8 x float> %arg2
ret <8 x float> %max
}
; CHECK-LABEL: ExeDepsFix_broadcastss_inreg
; CHECK: broadcastss
; CHECK: vandps
; CHECK: vmaxps
; CHECK: ret
define <4 x float> @ExeDepsFix_broadcastss_inreg(<4 x float> %arg, <4 x float> %arg2, i32 %broadcastvalue) {
%bitcast = bitcast <4 x float> %arg to <4 x i32>
%in = insertelement <4 x i32> undef, i32 %broadcastvalue, i32 0
%mask = shufflevector <4 x i32> %in, <4 x i32> undef, <4 x i32> zeroinitializer
%and = and <4 x i32> %bitcast, %mask
%floatcast = bitcast <4 x i32> %and to <4 x float>
%max_is_x = fcmp oge <4 x float> %floatcast, %arg2
%max = select <4 x i1> %max_is_x, <4 x float> %floatcast, <4 x float> %arg2
ret <4 x float> %max
}
; CHECK-LABEL: ExeDepsFix_broadcastss256_inreg
; CHECK: broadcastss
; CHECK: vandps
; CHECK: vmaxps
; CHECK: ret
define <8 x float> @ExeDepsFix_broadcastss256_inreg(<8 x float> %arg, <8 x float> %arg2, i32 %broadcastvalue) {
%bitcast = bitcast <8 x float> %arg to <8 x i32>
%in = insertelement <8 x i32> undef, i32 %broadcastvalue, i32 0
%mask = shufflevector <8 x i32> %in, <8 x i32> undef, <8 x i32> zeroinitializer
%and = and <8 x i32> %bitcast, %mask
%floatcast = bitcast <8 x i32> %and to <8 x float>
%max_is_x = fcmp oge <8 x float> %floatcast, %arg2
%max = select <8 x i1> %max_is_x, <8 x float> %floatcast, <8 x float> %arg2
ret <8 x float> %max
}
; CHECK-LABEL: ExeDepsFix_broadcastsd
; In that case the broadcast is directly folded into vandpd.
; CHECK: vandpd
; CHECK: vmaxpd
; CHECK:ret
define <2 x double> @ExeDepsFix_broadcastsd(<2 x double> %arg, <2 x double> %arg2) {
%bitcast = bitcast <2 x double> %arg to <2 x i64>
%and = and <2 x i64> %bitcast, <i64 2147483647, i64 2147483647>
%floatcast = bitcast <2 x i64> %and to <2 x double>
%max_is_x = fcmp oge <2 x double> %floatcast, %arg2
%max = select <2 x i1> %max_is_x, <2 x double> %floatcast, <2 x double> %arg2
ret <2 x double> %max
}
; CHECK-LABEL: ExeDepsFix_broadcastsd256
; CHECK: broadcastsd
; CHECK: vandpd
; CHECK: vmaxpd
; CHECK: ret
define <4 x double> @ExeDepsFix_broadcastsd256(<4 x double> %arg, <4 x double> %arg2) {
%bitcast = bitcast <4 x double> %arg to <4 x i64>
%and = and <4 x i64> %bitcast, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
%floatcast = bitcast <4 x i64> %and to <4 x double>
%max_is_x = fcmp oge <4 x double> %floatcast, %arg2
%max = select <4 x i1> %max_is_x, <4 x double> %floatcast, <4 x double> %arg2
ret <4 x double> %max
}
; CHECK-LABEL: ExeDepsFix_broadcastsd_inreg
[x86] Teach the target shuffle mask extraction to recognize unary forms of normally binary shuffle instructions like PUNPCKL and MOVLHPS. This detects cases where a single register is used for both operands making the shuffle behave in a unary way. We detect this and adjust the mask to use the unary form which allows the existing DAG combine for shuffle instructions to actually work at all. As a consequence, this uncovered a number of obvious bugs in the existing DAG combine which are fixed. It also now canonicalizes several shuffles even with the existing lowering. These typically are trying to match the shuffle to the domain of the input where before we only really modeled them with the floating point variants. All of the cases which change to an integer shuffle here have something in the integer domain, so there are no more or fewer domain crosses here AFAICT. Technically, it might be better to go from a GPR directly to the floating point domain, but detecting floating point *outputs* despite integer inputs is a lot more code and seems unlikely to be worthwhile in practice. If folks are seeing domain-crossing regressions here though, let me know and I can hack something up to fix it. Also as a consequence, a bunch of missed opportunities to form pshufb now can be formed. Notably, splats of i8s now form pshufb. Interestingly, this improves the existing splat lowering too. We go from 3 instructions to 1. Yes, we may tie up a register, but it seems very likely to be worth it, especially if splatting the 0th byte (the common case) as then we can use a zeroed register as the mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214625 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-02 10:27:38 +00:00
; ExeDepsFix works top down, thus it coalesces vpunpcklqdq domain with
; vpand and there is nothing more you can do to match vmaxpd.
[x86] Enable the new vector shuffle lowering by default. Update the entire regression test suite for the new shuffles. Remove most of the old testing which was devoted to the old shuffle lowering path and is no longer relevant really. Also remove a few other random tests that only really exercised shuffles and only incidently or without any interesting aspects to them. Benchmarking that I have done shows a few small regressions with this on LNT, zero measurable regressions on real, large applications, and for several benchmarks where the loop vectorizer fires in the hot path it shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy Bridge machines. Running on AMD machines shows even more dramatic improvements. When using newer ISA vector extensions the gains are much more modest, but the code is still better on the whole. There are a few regressions being tracked (PR21137, PR21138, PR21139) but by and large this is expected to be a win for x86 generated code performance. It is also more correct than the code it replaces. I have fuzz tested this extensively with ISA extensions up through AVX2 and found no crashes or miscompiles (yet...). The old lowering had a few miscompiles and crashers after a somewhat smaller amount of fuzz testing. There is one significant area where the new code path lags behind and that is in AVX-512 support. However, there was *extremely little* support for that already and so this isn't a significant step backwards and the new framework will probably make it easier to implement lowering that uses the full power of AVX-512's table-based shuffle+blend (IMO). Many thanks to Quentin, Andrea, Robert, and others for benchmarking assistance. Thanks to Adam and others for help with AVX-512. Thanks to Hal, Eric, and *many* others for answering my incessant questions about how the backend actually works. =] I will leave the old code path in the tree until the 3 PRs above are at least resolved to folks' satisfaction. Then I will rip it (and 1000s of lines of code) out. =] I don't expect this flag to stay around for very long. It may not survive next week. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-04 03:52:55 +00:00
; CHECK: vmovq
; CHECK: vpbroadcastq
; CHECK: vpand
; CHECK: vmaxpd
; CHECK: ret
define <2 x double> @ExeDepsFix_broadcastsd_inreg(<2 x double> %arg, <2 x double> %arg2, i64 %broadcastvalue) {
%bitcast = bitcast <2 x double> %arg to <2 x i64>
%in = insertelement <2 x i64> undef, i64 %broadcastvalue, i32 0
%mask = shufflevector <2 x i64> %in, <2 x i64> undef, <2 x i32> zeroinitializer
%and = and <2 x i64> %bitcast, %mask
%floatcast = bitcast <2 x i64> %and to <2 x double>
%max_is_x = fcmp oge <2 x double> %floatcast, %arg2
%max = select <2 x i1> %max_is_x, <2 x double> %floatcast, <2 x double> %arg2
ret <2 x double> %max
}
; CHECK-LABEL: ExeDepsFix_broadcastsd256_inreg
; CHECK: broadcastsd
; CHECK: vandpd
; CHECK: vmaxpd
; CHECK: ret
define <4 x double> @ExeDepsFix_broadcastsd256_inreg(<4 x double> %arg, <4 x double> %arg2, i64 %broadcastvalue) {
%bitcast = bitcast <4 x double> %arg to <4 x i64>
%in = insertelement <4 x i64> undef, i64 %broadcastvalue, i32 0
%mask = shufflevector <4 x i64> %in, <4 x i64> undef, <4 x i32> zeroinitializer
%and = and <4 x i64> %bitcast, %mask
%floatcast = bitcast <4 x i64> %and to <4 x double>
%max_is_x = fcmp oge <4 x double> %floatcast, %arg2
%max = select <4 x i1> %max_is_x, <4 x double> %floatcast, <4 x double> %arg2
ret <4 x double> %max
}