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llvm-6502/test/CodeGen/ARM/ldrd.ll

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Convert test to filecheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82835 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:41:17 +00:00
; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=V6
; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5
; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI
Part 1. - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
; rdar://r6949835
@b = external global i64*
define i64 @t(i64 %a) nounwind readonly {
entry:
Enable post-alloc scheduling for all ARM variants except for Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 06:11:08 +00:00
;V6: ldrd r2, [r2]
Convert test to filecheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82835 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:41:17 +00:00
Enable post-alloc scheduling for all ARM variants except for Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 06:11:08 +00:00
;V5: ldr r3, [r2]
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-17 17:52:21 +00:00
;V5: ldr r2, [r2, #4]
Convert test to filecheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82835 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:41:17 +00:00
Enable post-alloc scheduling for all ARM variants except for Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 06:11:08 +00:00
;EABI: ldr r3, [r2]
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-17 17:52:21 +00:00
;EABI: ldr r2, [r2, #4]
Convert test to filecheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82835 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:41:17 +00:00
Part 1. - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
%2 = mul i64 %1, %a
ret i64 %2
}
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