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llvm-6502/test/CodeGen/X86/vselect.ll

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llvm/test/CodeGen/X86/vselect.ll: Unbreak Windows x64 targets to add -mtriple=x86_64-unknown-unknown. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198114 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-28 13:04:29 +00:00
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR of ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-27 20:20:28 +00:00
; Verify that we don't emit packed vector shifts instructions if the
; condition used by the vector select is a vector of constants.
define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test1
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test2
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test3
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test4
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: movaps %xmm1, %xmm0
; CHECK: ret
define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test5
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
ret <8 x i16> %1
}
; CHECK-LABEL: test6
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test7
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test8
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test9
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: movaps %xmm1, %xmm0
; CHECK-NEXT: ret
define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test10
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test11
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test12
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test13
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK: ret
Teach the DAGCombiner how to fold 'vselect' dag nodes according to the following two rules: 1) fold (vselect (build_vector AllOnes), A, B) -> A 2) fold (vselect (build_vector AllZeros), A, B) -> B git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198777 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 18:33:04 +00:00
; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test14
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: pcmpeq
; CHECK: ret
define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test15
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: pcmpeq
; CHECK: ret
; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test16
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: ret
define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %1
}
; CHECK-LABEL: test17
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: ret
Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR of ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-27 20:20:28 +00:00
[X86] Teach how to combine a vselect into a movss/movsd Add target specific rules for combining vselect dag nodes into movss/movsd when possible. If the vector type of the vselect dag node in input is either MVT::v4i13 or MVT::v4f32, then try to fold according to rules: 1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B) 2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A) If the vector type of the vselect dag node in input is either MVT::v2i64 or MVT::v2f64 (and we have SSE2), then try to fold according to rules: 3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B) 4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199683 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 19:35:22 +00:00
define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test18
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: movss
; CHECK: ret
define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %1
}
; CHECK-LABEL: test19
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: movss
; CHECK: ret
define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
%1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
ret <2 x double> %1
}
; CHECK-LABEL: test20
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: movsd
; CHECK: ret
define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
%1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %1
}
; CHECK-LABEL: test21
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: movsd
; CHECK: ret
define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
ret <4 x float> %1
}
; CHECK-LABEL: test22
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: movss
; CHECK: ret
define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %1
}
; CHECK-LABEL: test23
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: movss
; CHECK: ret
define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
ret <2 x double> %1
}
; CHECK-LABEL: test24
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: movsd
; CHECK: ret
define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
%1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %1
}
; CHECK-LABEL: test25
; CHECK-NOT: psllw
; CHECK-NOT: psraw
; CHECK-NOT: xorps
; CHECK: movsd
; CHECK: ret
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