Add PowerPC intrinsics to support dcbz[l]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28696 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-06-06 21:29:23 +00:00
parent 73ebd0974c
commit 001db453f5
3 changed files with 34 additions and 0 deletions

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@ -15,6 +15,15 @@
// Definitions for all PowerPC intrinsics.
//
// Non-altivec intrinsics.
let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
// dcbz instruction.
def int_ppc_dcbz : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
// dcbzl (PPC970) instruction.
def int_ppc_dcbzl : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
}
let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
/// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> types,

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@ -325,6 +325,23 @@ class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
}
// DCB_Form - Form X instruction, used for dcb* instructions.
class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<31, OL, asmstr, itin> {
bits<5> A;
bits<5> B;
let Pattern = pattern;
let Inst{6-10} = immfield;
let Inst{11-15} = A;
let Inst{16-20} = B;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
// DSS_Form - Form X instruction, used for altivec dss* instructions.
class DSS_Form<bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>

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@ -318,6 +318,14 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7,
[(PPCbctrl)]>;
}
// DCB* instructions.
def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
"dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
PPC970_DGroup_Single;
def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
"dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
PPC970_DGroup_Single;
// D-Form instructions. Most instructions that perform an operation on a
// register and an immediate are of this type.
//