mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-24 06:30:19 +00:00
Model unpack lower and interleave as vector_shuffle so we can lower the
intrinsics as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27200 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
ef8ef91634
commit
0038e59803
@ -303,14 +303,18 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::LOAD, MVT::v8i16, Legal);
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setOperationAction(ISD::LOAD, MVT::v4i32, Legal);
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setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
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}
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computeRegisterProperties();
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@ -1499,6 +1503,29 @@ bool X86::isUNPCKHPDMask(SDNode *N) {
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cast<ConstantSDNode>(Bit1)->getValue() == 3);
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}
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/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKL.
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bool X86::isUNPCKLMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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unsigned NumElems = N->getNumOperands();
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if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
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return false;
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for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
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SDOperand BitI = N->getOperand(i);
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SDOperand BitI1 = N->getOperand(i+1);
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assert(isa<ConstantSDNode>(BitI) && isa<ConstantSDNode>(BitI1) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(BitI)->getValue() != j)
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return false;
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if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems)
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return false;
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}
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return true;
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}
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
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/// a splat of a single element.
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bool X86::isSplatMask(SDNode *N) {
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@ -2321,6 +2348,9 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType VT = Op.getValueType();
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unsigned NumElems = PermMask.getNumOperands();
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// All v2f64 cases are handled.
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if (NumElems == 2) return SDOperand();
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// Handle splat cases.
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if (X86::isSplatMask(PermMask.Val)) {
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if (V2.getOpcode() == ISD::UNDEF)
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@ -2332,8 +2362,8 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
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DAG.getNode(ISD::UNDEF, V1.getValueType()),
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PermMask);
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} else if (NumElems == 2) {
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// All v2f64 cases are handled.
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} else if (X86::isUNPCKLMask(PermMask.Val)) {
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// Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
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return SDOperand();
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} else if (X86::isPSHUFDMask(PermMask.Val)) {
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if (V2.getOpcode() == ISD::UNDEF)
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@ -2404,13 +2434,22 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
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// Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
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MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
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std::vector<SDOperand> MaskVec;
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for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
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MaskVec.push_back(DAG.getConstant(i, BaseVT));
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MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
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}
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SDOperand PermMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
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std::vector<SDOperand> V(NumElems);
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for (unsigned i = 0; i < NumElems; ++i)
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V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
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NumElems >>= 1;
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while (NumElems != 0) {
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for (unsigned i = 0; i < NumElems; ++i)
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V[i] = DAG.getNode(X86ISD::UNPCKL, VT, V[i], V[i + NumElems]);
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V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
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PermMask);
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NumElems >>= 1;
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}
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return V[0];
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@ -2453,7 +2492,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::Wrapper: return "X86ISD::Wrapper";
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case X86ISD::S2VEC: return "X86ISD::S2VEC";
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case X86ISD::ZEXT_S2VEC: return "X86ISD::ZEXT_S2VEC";
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case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
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}
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}
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@ -2543,5 +2581,6 @@ X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
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return (Mask.Val->getNumOperands() == 2 ||
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X86::isSplatMask(Mask.Val) ||
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X86::isPSHUFDMask(Mask.Val) ||
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X86::isSHUFPMask(Mask.Val));
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X86::isSHUFPMask(Mask.Val) ||
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X86::isUNPCKLMask(Mask.Val));
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}
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@ -153,10 +153,6 @@ namespace llvm {
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/// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination base
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/// does not have to match the operand type.
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ZEXT_S2VEC,
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/// UNPCKL - Unpack and interleave low. This corresponds to X86::UNPCKLPS,
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/// X86::PUNPCKL*.
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UNPCKL,
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};
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// X86 specific condition code. These correspond to X86_*_COND in
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@ -205,6 +201,10 @@ namespace llvm {
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/// specifies a shuffle of elements that is suitable for input to UNPCKHPD.
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bool isUNPCKHPDMask(SDNode *N);
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/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKL.
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bool isUNPCKLMask(SDNode *N);
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element.
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bool isSplatMask(SDNode *N);
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@ -30,8 +30,6 @@ def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
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def SDTUnpckl : SDTypeProfile<1, 2,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
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def X86unpckl : SDNode<"X86ISD::UNPCKL", SDTUnpckl,
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[]>;
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//===----------------------------------------------------------------------===//
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// SSE pattern fragments
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@ -77,6 +75,10 @@ def UNPCKHPD_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKHPDMask(N);
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}], SHUFFLE_get_shuf_imm>;
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def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKLMask(N);
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}]>;
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// Only use PSHUF if it is not a splat.
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def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
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return !X86::isSplatMask(N) && X86::isPSHUFDMask(N);
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@ -756,14 +758,17 @@ def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
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let isTwoAddress = 1 in {
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def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst, (vector_shuffle
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(v4f32 VR128:$src1), (v4f32 VR128:$src2),
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SHUFP_shuffle_mask:$src3))]>;
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def SHUFPSrm : PSIi8<0xC6, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst, (vector_shuffle
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(v4f32 VR128:$src1), (load addr:$src2),
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SHUFP_shuffle_mask:$src3))]>;
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def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
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@ -772,7 +777,10 @@ def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
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SHUFP_shuffle_mask:$src3))]>;
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def SHUFPDrm : PDIi8<0xC6, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst, (vector_shuffle
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(v2f64 VR128:$src1), (load addr:$src2),
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SHUFP_shuffle_mask:$src3))]>;
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def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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@ -789,13 +797,15 @@ def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
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def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"unpcklps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4f32 (X86unpckl VR128:$src1,
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VR128:$src2)))]>;
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"unpcklps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4f32 (X86unpckl VR128:$src1,
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(load addr:$src2))))]>;
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"unpcklpd {$src2, $dst|$dst, $src2}", []>;
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@ -895,33 +905,39 @@ def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"punpcklbw {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v16i8 (X86unpckl VR128:$src1,
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VR128:$src2)))]>;
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[(set VR128:$dst,
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(v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpcklbw {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v16i8 (X86unpckl VR128:$src1,
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(load addr:$src2))))]>;
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[(set VR128:$dst,
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(v16i8 (vector_shuffle VR128:$src1, (load addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"punpcklwd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v8i16 (X86unpckl VR128:$src1,
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VR128:$src2)))]>;
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[(set VR128:$dst,
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(v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpcklwd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v8i16 (X86unpckl VR128:$src1,
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(load addr:$src2))))]>;
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[(set VR128:$dst,
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(v8i16 (vector_shuffle VR128:$src1, (load addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"punpckldq {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4i32 (X86unpckl VR128:$src1,
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VR128:$src2)))]>;
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[(set VR128:$dst,
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(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpckldq {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v4i32 (X86unpckl VR128:$src1,
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(load addr:$src2))))]>;
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[(set VR128:$dst,
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(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"punpcklqdq {$src2, $dst|$dst, $src2}", []>;
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