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Fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28311 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1307,7 +1307,7 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
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unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
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enum {
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OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
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OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
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OP_VMRGHW,
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OP_VMRGLW,
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OP_VSPLTISW0,
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@ -1978,9 +1978,9 @@ PPCTargetLowering::LowerCallTo(SDOperand Chain,
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// free GPRs, then we can pass both halves of the i64 in registers.
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if (GPR_remaining > 0) {
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
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Args[i].first, DAG.getConstant(1, MVT::i32));
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Args[i].first, DAG.getConstant(1, MVT::i32));
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
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Args[i].first, DAG.getConstant(0, MVT::i32));
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Args[i].first, DAG.getConstant(0, MVT::i32));
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args_to_use.push_back(Hi);
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--GPR_remaining;
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if (GPR_remaining > 0) {
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