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[x86] Fix register class of folded load index reg.

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When folding a load in to another instruction, we need to fix the class of the index register
Otherwise, it could be something like GR64 not GR64_NOSP and would fail the machine verifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236644 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pete Cooper 2015-05-06 21:37:19 +00:00
parent d71e55b97f
commit 0040d179d2
2 changed files with 37 additions and 0 deletions
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17
lib/Target/X86/X86FastISel.cpp
View File

@ -3534,6 +3534,23 @@ bool X86FastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
if (!Result)
return false;
// The index register could be in the wrong register class. Unfortunately,
// foldMemoryOperandImpl could have commuted the instruction so its not enough
// to just look at OpNo + the offset to the index reg. We actually need to
// scan the instruction to find the index reg and see if its the correct reg
// class.
for (MIOperands MO(Result); MO.isValid(); ++MO) {
if (!MO->isReg() || MO->isDef() || MO->getReg() != AM.IndexReg)
continue;
// Found the index reg, now try to rewrite it.
unsigned OpNo = MO.getOperandNo();
unsigned IndexReg = constrainOperandRegClass(Result->getDesc(),
MO->getReg(), OpNo);
if (IndexReg == MO->getReg())
continue;
MO->setReg(IndexReg);
}
Result->addMemOperand(*FuncInfo.MF, createMachineMemOperandFor(LI));
FuncInfo.MBB->insert(FuncInfo.InsertPt, Result);
MI->eraseFromParent();

20
test/CodeGen/X86/fast-isel-movsbl-indexreg.ll Normal file
View File

@ -0,0 +1,20 @@
; RUN: llc %s -o - -verify-machineinstrs -fast-isel=true | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown"
; The index register on the folded memory operand was incorrect. Ensure we generate
; movsbl in fast-isel, but also that it passes verification which will check the register
; class.
; CHECK: movsbl
@table = external hidden global [64 x i8], align 16
define i32 @test(i32 %x, i64 %offset) {
bb:
%tmp37 = getelementptr inbounds [64 x i8], [64 x i8]* @table, i64 0, i64 %offset
%tmp38 = load i8, i8* %tmp37, align 1
%tmp39 = sext i8 %tmp38 to i32
ret i32 %tmp39
}