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[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -91,6 +91,10 @@ class MipsAsmParser : public MCTargetAsmParser {
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parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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int RegKind);
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int RegKind);
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MipsAsmParser::OperandMatchResultTy
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parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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int RegKind);
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::OperandMatchResultTy
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parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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@ -150,6 +154,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::OperandMatchResultTy
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parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MipsAsmParser::OperandMatchResultTy
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parseMSA128CtrlRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::OperandMatchResultTy
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parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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@ -228,6 +235,8 @@ class MipsAsmParser : public MCTargetAsmParser {
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int matchMSA128RegisterName(StringRef Name);
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int matchMSA128RegisterName(StringRef Name);
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int matchMSA128CtrlRegisterName(StringRef Name);
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int regKindToRegClass(int RegKind);
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int regKindToRegClass(int RegKind);
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unsigned getReg(int RC, int RegNo);
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unsigned getReg(int RC, int RegNo);
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@ -282,7 +291,8 @@ public:
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Kind_MSA128BRegs,
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Kind_MSA128BRegs,
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Kind_MSA128HRegs,
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Kind_MSA128HRegs,
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Kind_MSA128WRegs,
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Kind_MSA128WRegs,
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Kind_MSA128DRegs
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Kind_MSA128DRegs,
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Kind_MSA128CtrlRegs
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};
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};
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private:
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private:
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@ -521,6 +531,10 @@ public:
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return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
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return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
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}
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}
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bool isMSA128CRAsm() const {
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return Kind == k_Register && Reg.Kind == Kind_MSA128CtrlRegs;
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}
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/// getStartLoc - Get the location of the first token of this operand.
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const {
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SMLoc getStartLoc() const {
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return StartLoc;
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return StartLoc;
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@ -982,6 +996,23 @@ int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
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return IntVal;
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return IntVal;
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}
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}
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int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
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int CC;
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CC = StringSwitch<unsigned>(Name)
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.Case("msair", 0)
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.Case("msacsr", 1)
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.Case("msaaccess", 2)
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.Case("msasave", 3)
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.Case("msamodify", 4)
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.Case("msarequest", 5)
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.Case("msamap", 6)
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.Case("msaunmap", 7)
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.Default(-1);
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return CC;
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}
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int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
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int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
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int CC;
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int CC;
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@ -1014,6 +1045,7 @@ int MipsAsmParser::regKindToRegClass(int RegKind) {
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case MipsOperand::Kind_MSA128HRegs: return Mips::MSA128HRegClassID;
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case MipsOperand::Kind_MSA128HRegs: return Mips::MSA128HRegClassID;
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case MipsOperand::Kind_MSA128WRegs: return Mips::MSA128WRegClassID;
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case MipsOperand::Kind_MSA128WRegs: return Mips::MSA128WRegClassID;
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case MipsOperand::Kind_MSA128DRegs: return Mips::MSA128DRegClassID;
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case MipsOperand::Kind_MSA128DRegs: return Mips::MSA128DRegClassID;
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case MipsOperand::Kind_MSA128CtrlRegs: return Mips::MSACtrlRegClassID;
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default :return -1;
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default :return -1;
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}
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}
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@ -1714,6 +1746,45 @@ MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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return MatchOperand_Success;
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return MatchOperand_Success;
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}
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
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int RegKind) {
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MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
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if (Kind != MipsOperand::Kind_MSA128CtrlRegs)
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return MatchOperand_NoMatch;
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if (Parser.getTok().isNot(AsmToken::Dollar))
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return MatchOperand_ParseFail;
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SMLoc S = Parser.getTok().getLoc();
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Parser.Lex(); // Eat the '$' symbol.
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int RegNum = -1;
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if (getLexer().getKind() == AsmToken::Identifier)
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RegNum = matchMSA128CtrlRegisterName(Parser.getTok().getString().lower());
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else if (getLexer().getKind() == AsmToken::Integer)
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RegNum = Parser.getTok().getIntVal();
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else
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return MatchOperand_ParseFail;
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if (RegNum < 0 || RegNum > 7)
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return MatchOperand_ParseFail;
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int RegVal = getReg(regKindToRegClass(Kind), RegNum);
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if (RegVal == -1)
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return MatchOperand_ParseFail;
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MipsOperand *RegOp = MipsOperand::CreateReg(RegVal, S,
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Parser.getTok().getLoc());
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RegOp->setRegKind(MipsOperand::Kind_MSA128CtrlRegs);
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Operands.push_back(RegOp);
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Parser.Lex(); // Eat the register identifier.
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return MatchOperand_Success;
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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@ -1878,6 +1949,12 @@ MipsAsmParser::parseMSA128DRegs(
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return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128DRegs);
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return parseMSARegs(Operands, (int) MipsOperand::Kind_MSA128DRegs);
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}
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseMSA128CtrlRegs(
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SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
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return parseMSACtrlRegs(Operands, (int) MipsOperand::Kind_MSA128CtrlRegs);
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}
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bool MipsAsmParser::searchSymbolAlias(
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bool MipsAsmParser::searchSymbolAlias(
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SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
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SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
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@ -190,6 +190,11 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
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uint64_t Address,
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uint64_t Address,
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const void *Decoder);
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const void *Decoder);
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static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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unsigned Offset,
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uint64_t Address,
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uint64_t Address,
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@ -688,6 +693,18 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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}
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}
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static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 7)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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unsigned Offset,
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uint64_t Address,
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uint64_t Address,
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@ -150,6 +150,26 @@ class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
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let Inst{5-0} = minor;
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let Inst{5-0} = minor;
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}
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}
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class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
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bits<5> rd;
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bits<5> cs;
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let Inst{25-16} = major;
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let Inst{15-11} = cs;
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let Inst{10-6} = rd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
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bits<5> rs;
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bits<5> cd;
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let Inst{25-16} = major;
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let Inst{15-11} = rs;
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let Inst{10-6} = cd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
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class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<4> n;
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bits<4> n;
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bits<5> ws;
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bits<5> ws;
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@ -470,7 +470,7 @@ class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
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class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
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class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
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class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
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class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
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class CFCMSA_ENC : MSA_ELM_FMT<0b0001111110, 0b011001>;
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class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
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class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
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class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
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class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
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class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
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@ -520,7 +520,7 @@ class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
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class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
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class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
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class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
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class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
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class CTCMSA_ENC : MSA_ELM_FMT<0b0000111110, 0b011001>;
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class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
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class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
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class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
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class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
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class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
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@ -1582,8 +1582,8 @@ class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
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MSA128DOpnd>;
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MSA128DOpnd>;
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class CFCMSA_DESC {
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class CFCMSA_DESC {
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dag OutOperandList = (outs GPR32:$rd);
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dag OutOperandList = (outs GPR32Opnd:$rd);
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dag InOperandList = (ins MSACtrl:$cs);
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dag InOperandList = (ins MSA128CROpnd:$cs);
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string AsmString = "cfcmsa\t$rd, $cs";
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string AsmString = "cfcmsa\t$rd, $cs";
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InstrItinClass Itinerary = NoItinerary;
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InstrItinClass Itinerary = NoItinerary;
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bit hasSideEffects = 1;
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bit hasSideEffects = 1;
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@ -1666,7 +1666,7 @@ class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
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class CTCMSA_DESC {
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class CTCMSA_DESC {
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dag OutOperandList = (outs);
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dag OutOperandList = (outs);
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dag InOperandList = (ins MSACtrl:$cd, GPR32:$rs);
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dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
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string AsmString = "ctcmsa\t$cd, $rs";
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string AsmString = "ctcmsa\t$cd, $rs";
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InstrItinClass Itinerary = NoItinerary;
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InstrItinClass Itinerary = NoItinerary;
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bit hasSideEffects = 1;
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bit hasSideEffects = 1;
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@ -237,14 +237,14 @@ let Namespace = "Mips" in {
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DSPOutFlag23]>;
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DSPOutFlag23]>;
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// MSA-ASE control registers.
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// MSA-ASE control registers.
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def MSAIR : Register<"0">;
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def MSAIR : MipsReg<0, "0">;
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def MSACSR : Register<"1">;
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def MSACSR : MipsReg<1, "1">;
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def MSAAccess : Register<"2">;
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def MSAAccess : MipsReg<2, "2">;
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def MSASave : Register<"3">;
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def MSASave : MipsReg<3, "3">;
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def MSAModify : Register<"4">;
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def MSAModify : MipsReg<4, "4">;
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def MSARequest : Register<"5">;
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def MSARequest : MipsReg<5, "5">;
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def MSAMap : Register<"6">;
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def MSAMap : MipsReg<6, "6">;
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def MSAUnmap : Register<"7">;
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def MSAUnmap : MipsReg<7, "7">;
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -456,6 +456,11 @@ def MSA128DAsmOperand : MipsAsmRegOperand {
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let ParserMethod = "parseMSA128DRegs";
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let ParserMethod = "parseMSA128DRegs";
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}
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}
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def MSA128CRAsmOperand : MipsAsmRegOperand {
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let Name = "MSA128CRAsm";
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let ParserMethod = "parseMSA128CtrlRegs";
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}
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def GPR32Opnd : RegisterOperand<GPR32> {
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def GPR32Opnd : RegisterOperand<GPR32> {
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let ParserMatchClass = GPR32AsmOperand;
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let ParserMatchClass = GPR32AsmOperand;
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}
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}
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@ -538,3 +543,7 @@ def MSA128DOpnd : RegisterOperand<MSA128D> {
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let ParserMatchClass = MSA128DAsmOperand;
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let ParserMatchClass = MSA128DAsmOperand;
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}
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}
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def MSA128CROpnd : RegisterOperand<MSACtrl> {
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let ParserMatchClass = MSA128CRAsmOperand;
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}
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105
test/MC/Mips/msa/test_ctrlregs.s
Normal file
105
test/MC/Mips/msa/test_ctrlregs.s
Normal file
@ -0,0 +1,105 @@
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
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#
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
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#
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||||||
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#CHECK: cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59]
|
||||||
|
#CHECK: cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59]
|
||||||
|
#CHECK: cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99]
|
||||||
|
#CHECK: cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99]
|
||||||
|
#CHECK: cfcmsa $3, $2 # encoding: [0x78,0x7e,0x10,0xd9]
|
||||||
|
#CHECK: cfcmsa $3, $2 # encoding: [0x78,0x7e,0x10,0xd9]
|
||||||
|
#CHECK: cfcmsa $4, $3 # encoding: [0x78,0x7e,0x19,0x19]
|
||||||
|
#CHECK: cfcmsa $4, $3 # encoding: [0x78,0x7e,0x19,0x19]
|
||||||
|
#CHECK: cfcmsa $5, $4 # encoding: [0x78,0x7e,0x21,0x59]
|
||||||
|
#CHECK: cfcmsa $5, $4 # encoding: [0x78,0x7e,0x21,0x59]
|
||||||
|
#CHECK: cfcmsa $6, $5 # encoding: [0x78,0x7e,0x29,0x99]
|
||||||
|
#CHECK: cfcmsa $6, $5 # encoding: [0x78,0x7e,0x29,0x99]
|
||||||
|
#CHECK: cfcmsa $7, $6 # encoding: [0x78,0x7e,0x31,0xd9]
|
||||||
|
#CHECK: cfcmsa $7, $6 # encoding: [0x78,0x7e,0x31,0xd9]
|
||||||
|
#CHECK: cfcmsa $8, $7 # encoding: [0x78,0x7e,0x3a,0x19]
|
||||||
|
#CHECK: cfcmsa $8, $7 # encoding: [0x78,0x7e,0x3a,0x19]
|
||||||
|
|
||||||
|
#CHECK: ctcmsa $0, $1 # encoding: [0x78,0x3e,0x08,0x19]
|
||||||
|
#CHECK: ctcmsa $0, $1 # encoding: [0x78,0x3e,0x08,0x19]
|
||||||
|
#CHECK: ctcmsa $1, $2 # encoding: [0x78,0x3e,0x10,0x59]
|
||||||
|
#CHECK: ctcmsa $1, $2 # encoding: [0x78,0x3e,0x10,0x59]
|
||||||
|
#CHECK: ctcmsa $2, $3 # encoding: [0x78,0x3e,0x18,0x99]
|
||||||
|
#CHECK: ctcmsa $2, $3 # encoding: [0x78,0x3e,0x18,0x99]
|
||||||
|
#CHECK: ctcmsa $3, $4 # encoding: [0x78,0x3e,0x20,0xd9]
|
||||||
|
#CHECK: ctcmsa $3, $4 # encoding: [0x78,0x3e,0x20,0xd9]
|
||||||
|
#CHECK: ctcmsa $4, $5 # encoding: [0x78,0x3e,0x29,0x19]
|
||||||
|
#CHECK: ctcmsa $4, $5 # encoding: [0x78,0x3e,0x29,0x19]
|
||||||
|
#CHECK: ctcmsa $5, $6 # encoding: [0x78,0x3e,0x31,0x59]
|
||||||
|
#CHECK: ctcmsa $5, $6 # encoding: [0x78,0x3e,0x31,0x59]
|
||||||
|
#CHECK: ctcmsa $6, $7 # encoding: [0x78,0x3e,0x39,0x99]
|
||||||
|
#CHECK: ctcmsa $6, $7 # encoding: [0x78,0x3e,0x39,0x99]
|
||||||
|
#CHECK: ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9]
|
||||||
|
#CHECK: ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9]
|
||||||
|
|
||||||
|
#CHECKOBJDUMP: cfcmsa $1, $0
|
||||||
|
#CHECKOBJDUMP: cfcmsa $1, $0
|
||||||
|
#CHECKOBJDUMP: cfcmsa $2, $1
|
||||||
|
#CHECKOBJDUMP: cfcmsa $2, $1
|
||||||
|
#CHECKOBJDUMP: cfcmsa $3, $2
|
||||||
|
#CHECKOBJDUMP: cfcmsa $3, $2
|
||||||
|
#CHECKOBJDUMP: cfcmsa $4, $3
|
||||||
|
#CHECKOBJDUMP: cfcmsa $4, $3
|
||||||
|
#CHECKOBJDUMP: cfcmsa $5, $4
|
||||||
|
#CHECKOBJDUMP: cfcmsa $5, $4
|
||||||
|
#CHECKOBJDUMP: cfcmsa $6, $5
|
||||||
|
#CHECKOBJDUMP: cfcmsa $6, $5
|
||||||
|
#CHECKOBJDUMP: cfcmsa $7, $6
|
||||||
|
#CHECKOBJDUMP: cfcmsa $7, $6
|
||||||
|
#CHECKOBJDUMP: cfcmsa $8, $7
|
||||||
|
#CHECKOBJDUMP: cfcmsa $8, $7
|
||||||
|
|
||||||
|
#CHECKOBJDUMP: ctcmsa $0, $1
|
||||||
|
#CHECKOBJDUMP: ctcmsa $0, $1
|
||||||
|
#CHECKOBJDUMP: ctcmsa $1, $2
|
||||||
|
#CHECKOBJDUMP: ctcmsa $1, $2
|
||||||
|
#CHECKOBJDUMP: ctcmsa $2, $3
|
||||||
|
#CHECKOBJDUMP: ctcmsa $2, $3
|
||||||
|
#CHECKOBJDUMP: ctcmsa $3, $4
|
||||||
|
#CHECKOBJDUMP: ctcmsa $3, $4
|
||||||
|
#CHECKOBJDUMP: ctcmsa $4, $5
|
||||||
|
#CHECKOBJDUMP: ctcmsa $4, $5
|
||||||
|
#CHECKOBJDUMP: ctcmsa $5, $6
|
||||||
|
#CHECKOBJDUMP: ctcmsa $5, $6
|
||||||
|
#CHECKOBJDUMP: ctcmsa $6, $7
|
||||||
|
#CHECKOBJDUMP: ctcmsa $6, $7
|
||||||
|
#CHECKOBJDUMP: ctcmsa $7, $8
|
||||||
|
#CHECKOBJDUMP: ctcmsa $7, $8
|
||||||
|
|
||||||
|
cfcmsa $1, $msair
|
||||||
|
cfcmsa $1, $0
|
||||||
|
cfcmsa $2, $msacsr
|
||||||
|
cfcmsa $2, $1
|
||||||
|
cfcmsa $3, $msaaccess
|
||||||
|
cfcmsa $3, $2
|
||||||
|
cfcmsa $4, $msasave
|
||||||
|
cfcmsa $4, $3
|
||||||
|
cfcmsa $5, $msamodify
|
||||||
|
cfcmsa $5, $4
|
||||||
|
cfcmsa $6, $msarequest
|
||||||
|
cfcmsa $6, $5
|
||||||
|
cfcmsa $7, $msamap
|
||||||
|
cfcmsa $7, $6
|
||||||
|
cfcmsa $8, $msaunmap
|
||||||
|
cfcmsa $8, $7
|
||||||
|
|
||||||
|
ctcmsa $msair, $1
|
||||||
|
ctcmsa $0, $1
|
||||||
|
ctcmsa $msacsr, $2
|
||||||
|
ctcmsa $1, $2
|
||||||
|
ctcmsa $msaaccess, $3
|
||||||
|
ctcmsa $2, $3
|
||||||
|
ctcmsa $msasave, $4
|
||||||
|
ctcmsa $3, $4
|
||||||
|
ctcmsa $msamodify, $5
|
||||||
|
ctcmsa $4, $5
|
||||||
|
ctcmsa $msarequest, $6
|
||||||
|
ctcmsa $5, $6
|
||||||
|
ctcmsa $msamap, $7
|
||||||
|
ctcmsa $6, $7
|
||||||
|
ctcmsa $msaunmap, $8
|
||||||
|
ctcmsa $7, $8
|
Loading…
Reference in New Issue
Block a user