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Shrink Thumb2 movcc instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78790 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1225,7 +1225,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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break;
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case MVT::i32:
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Opc = Subtarget->isThumb()
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? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
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? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
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: ARM::MOVCCr;
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break;
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case MVT::f32:
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@ -2539,7 +2539,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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switch (MI->getOpcode()) {
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default:
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llvm_unreachable("Unexpected instr type to insert");
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case ARM::tMOVCCr: {
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case ARM::tMOVCCr_pseudo: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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@ -611,13 +611,20 @@ def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
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// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
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// Expanded by the scheduler into a branch sequence.
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// FIXME: Add actual movcc in IT blocks for Thumb2.
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let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
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def tMOVCCr :
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def tMOVCCr_pseudo :
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PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
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NoItinerary, "@ tMOVCCr $cc",
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[/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
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// 16-bit movcc in IT blocks for Thumb2.
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def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
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"mov", " $dst, $rhs", []>;
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def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
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"mov", " $dst, $rhs", []>;
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// tLEApcrel - Load a pc-relative address into a register without offending the
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// assembler.
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def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
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@ -77,8 +77,9 @@ namespace {
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{ ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
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// FIXME: Do we need the 16-bit 'S' variant?
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// FIXME: t2MOVcc
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{ ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 },
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{ ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0 },
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{ ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 0, 0,1, 0 },
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{ ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 0 },
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