From 009d3f400cf0538be8369d17b76092817261585f Mon Sep 17 00:00:00 2001
From: Misha Brukman <brukman+llvm@gmail.com>
Date: Thu, 14 Oct 2004 21:57:19 +0000
Subject: [PATCH] Generate the SparcV8 code emitter from .td files

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17000 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Sparc/Makefile   | 6 +++++-
 lib/Target/SparcV8/Makefile | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile
index 31d379ae0e0..5528a3547b9 100644
--- a/lib/Target/Sparc/Makefile
+++ b/lib/Target/Sparc/Makefile
@@ -16,7 +16,7 @@ TDFILE  := $(SourceDir)/SparcV8.td
 # Make sure that tblgen is run, first thing.
 $(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
                  SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
-                 SparcV8GenInstrInfo.inc
+                 SparcV8GenInstrInfo.inc SparcV8GenCodeEmitter.inc
 
 SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
 	@echo "Building SparcV8.td register names with tblgen"
@@ -38,5 +38,9 @@ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
 	@echo "Building SparcV8.td instruction information with tblgen"
 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
 
+SparcV8GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN)
+	@echo "Building SparcV8.td code emitter with tblgen"
+	$(VERB) $(TBLGEN) -I $(SourceDir) $(TDFILE) -gen-emitter -o $@
+
 clean::
 	$(VERB) rm -f *.inc
diff --git a/lib/Target/SparcV8/Makefile b/lib/Target/SparcV8/Makefile
index 31d379ae0e0..5528a3547b9 100644
--- a/lib/Target/SparcV8/Makefile
+++ b/lib/Target/SparcV8/Makefile
@@ -16,7 +16,7 @@ TDFILE  := $(SourceDir)/SparcV8.td
 # Make sure that tblgen is run, first thing.
 $(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
                  SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
-                 SparcV8GenInstrInfo.inc
+                 SparcV8GenInstrInfo.inc SparcV8GenCodeEmitter.inc
 
 SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
 	@echo "Building SparcV8.td register names with tblgen"
@@ -38,5 +38,9 @@ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
 	@echo "Building SparcV8.td instruction information with tblgen"
 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
 
+SparcV8GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN)
+	@echo "Building SparcV8.td code emitter with tblgen"
+	$(VERB) $(TBLGEN) -I $(SourceDir) $(TDFILE) -gen-emitter -o $@
+
 clean::
 	$(VERB) rm -f *.inc