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Thumb2 encodings for MSR and MRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120309 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -3212,8 +3212,14 @@ def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
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// Move between special register and ARM core register -- for disassembly only
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// Move between special register and ARM core register -- for disassembly only
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//
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//
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// Rd = Instr{11-8}
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class T2MRS<dag oops, dag iops, InstrItinClass itin,
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def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rd;
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let Inst{11-8} = Rd{3-0};
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}
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def t2MRS : T2MRS<(outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
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[/* For disassembly only; pattern left blank */]> {
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{31-27} = 0b11110;
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let Inst{26} = 0;
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let Inst{26} = 0;
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@@ -3223,8 +3229,8 @@ def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
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let Inst{12} = 0;
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let Inst{12} = 0;
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}
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}
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// Rd = Instr{11-8}
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def t2MRSsys : T2MRS<
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def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
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(outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
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[/* For disassembly only; pattern left blank */]> {
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{31-27} = 0b11110;
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let Inst{26} = 0;
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let Inst{26} = 0;
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@@ -3234,9 +3240,17 @@ def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
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let Inst{12} = 0;
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let Inst{12} = 0;
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}
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}
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// Rn = Inst{19-16}
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class T2MSR<dag oops, dag iops, InstrItinClass itin,
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def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
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string opc, string asm, list<dag> pattern>
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"\tcpsr$mask, $src",
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rn;
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bits<4> mask;
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let Inst{19-16} = Rn{3-0};
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let Inst{11-8} = mask{3-0};
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}
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def t2MSR : T2MSR<(outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
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"\tcpsr$mask, $Rn",
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[/* For disassembly only; pattern left blank */]> {
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{31-27} = 0b11110;
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let Inst{26} = 0;
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let Inst{26} = 0;
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@@ -3246,9 +3260,9 @@ def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
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let Inst{12} = 0;
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let Inst{12} = 0;
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}
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}
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// Rn = Inst{19-16}
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def t2MSRsys : T2MSR<
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def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
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(outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
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"\tspsr$mask, $src",
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"\tspsr$mask, $Rn",
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[/* For disassembly only; pattern left blank */]> {
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{31-27} = 0b11110;
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let Inst{26} = 0;
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let Inst{26} = 0;
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