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Run codegen dce pass for all targets at all optimization levels. Previously it's

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only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95493 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-02-06 09:07:11 +00:00
parent e3e86dce64
commit 00a99a3584
16 changed files with 83 additions and 248 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/DeadMachineInstructionElim.cpp
View File

@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "codegen-dce"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Pass.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@ -19,8 +20,11 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/Statistic.h"
using namespace llvm;
STATISTIC(NumDeletes, "Number of dead instructions deleted");
namespace {
class DeadMachineInstructionElim : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
@ -126,6 +130,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
AnyChanges = true;
MI->eraseFromParent();
++NumDeletes;
MIE = MBB->rend();
// MII is now pointing to the next instruction to process,
// so don't increment it.

6
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -291,6 +291,12 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM, "After Instruction Selection",
/* allowDoubleDefs= */ true);
// Delete dead machine instructions regardless of optimization level.
PM.add(createDeadMachineInstructionElimPass());
printAndVerify(PM, "After codegen DCE pass",
/* allowDoubleDefs= */ true);
if (OptLevel != CodeGenOpt::None) {
PM.add(createOptimizeExtsPass());
if (!DisableMachineLICM)

3
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -671,6 +671,9 @@ void LiveIntervals::computeIntervals() {
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = MBBI;
if (MBB->empty())
continue;
// Track the index of the current machine instr.
SlotIndex MIIndex = getMBBStartIdx(MBB);
DEBUG(dbgs() << MBB->getName() << ":\n");

4
lib/Target/X86/X86TargetMachine.cpp
View File

@ -148,10 +148,6 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
// Install an instruction selector.
PM.add(createX86ISelDag(*this, OptLevel));
// If we're using Fast-ISel, clean up the mess.
if (EnableFastISel)
PM.add(createDeadMachineInstructionElimPass());
// Install a pass to insert x87 FP_REG_KILL instructions, as needed.
PM.add(createX87FPRegKillInserterPass());

4
test/CodeGen/ARM/2009-10-30.ll
View File

@ -5,8 +5,8 @@
define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) {
entry:
;CHECK: sub sp, sp, #4
;CHECK: add r0, sp, #8
;CHECK: str r0, [sp], #+4
;CHECK: add r{{[0-9]+}}, sp, #8
;CHECK: str r{{[0-9]+}}, [sp], #+4
;CHECK: bx lr
%ap = alloca i8*, align 4
%ap1 = bitcast i8** %ap to i8*

8
test/CodeGen/ARM/long_shift.ll
View File

@ -23,10 +23,10 @@ define i32 @f1(i64 %x, i64 %y) {
define i32 @f2(i64 %x, i64 %y) {
; CHECK: f2
; CHECK: mov r0, r0, lsr r2
; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: rsb r12, r2, #32
; CHECK-NEXT: sub r2, r2, #32
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: orr r0, r0, r1, lsl r12
; CHECK-NEXT: movge r0, r1, asr r2
%a = ashr i64 %x, %y
%b = trunc i64 %a to i32
@ -36,10 +36,10 @@ define i32 @f2(i64 %x, i64 %y) {
define i32 @f3(i64 %x, i64 %y) {
; CHECK: f3
; CHECK: mov r0, r0, lsr r2
; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: rsb r12, r2, #32
; CHECK-NEXT: sub r2, r2, #32
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: orr r0, r0, r1, lsl r12
; CHECK-NEXT: movge r0, r1, lsr r2
%a = lshr i64 %x, %y
%b = trunc i64 %a to i32

65
test/CodeGen/ARM/remat-2.ll
View File

@ -1,65 +0,0 @@
; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization"
define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
entry:
br i1 undef, label %smvp.exit, label %bb.i3
bb.i3: ; preds = %bb.i3, %bb134
br i1 undef, label %smvp.exit, label %bb.i3
smvp.exit: ; preds = %bb.i3
%0 = fmul double undef, 2.400000e-03 ; <double> [#uses=2]
br i1 undef, label %bb138.preheader, label %bb159
bb138.preheader: ; preds = %smvp.exit
br label %bb138
bb138: ; preds = %bb138, %bb138.preheader
br i1 undef, label %bb138, label %bb145.loopexit
bb142: ; preds = %bb.nph218.bb.nph218.split_crit_edge, %phi0.exit
%1 = fmul double undef, -1.200000e-03 ; <double> [#uses=1]
%2 = fadd double undef, %1 ; <double> [#uses=1]
%3 = fmul double %2, undef ; <double> [#uses=1]
%4 = fsub double 0.000000e+00, %3 ; <double> [#uses=1]
br i1 %14, label %phi1.exit, label %bb.i35
bb.i35: ; preds = %bb142
%5 = call arm_apcscc double @sin(double %15) nounwind readonly ; <double> [#uses=1]
%6 = fmul double %5, 0x4031740AFA84AD8A ; <double> [#uses=1]
%7 = fsub double 1.000000e+00, undef ; <double> [#uses=1]
%8 = fdiv double %7, 6.000000e-01 ; <double> [#uses=1]
br label %phi1.exit
phi1.exit: ; preds = %bb.i35, %bb142
%.pn = phi double [ %6, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=0]
%9 = phi double [ %8, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=1]
%10 = fmul double undef, %9 ; <double> [#uses=0]
br i1 %14, label %phi0.exit, label %bb.i
bb.i: ; preds = %phi1.exit
unreachable
phi0.exit: ; preds = %phi1.exit
%11 = fsub double %4, undef ; <double> [#uses=1]
%12 = fadd double 0.000000e+00, %11 ; <double> [#uses=1]
store double %12, double* undef, align 4
br label %bb142
bb145.loopexit: ; preds = %bb138
br i1 undef, label %bb.nph218.bb.nph218.split_crit_edge, label %bb159
bb.nph218.bb.nph218.split_crit_edge: ; preds = %bb145.loopexit
%13 = fmul double %0, 0x401921FB54442D18 ; <double> [#uses=1]
%14 = fcmp ugt double %0, 6.000000e-01 ; <i1> [#uses=2]
%15 = fdiv double %13, 6.000000e-01 ; <double> [#uses=1]
br label %bb142
bb159: ; preds = %bb145.loopexit, %smvp.exit, %bb134
unreachable
bb166: ; preds = %bb127
unreachable
}
declare arm_apcscc double @sin(double) nounwind readonly

152
test/CodeGen/ARM/remat.ll
View File

@ -1,119 +1,65 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 3
; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization"
%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
%struct.LOCBOX = type { i32, i32, i32, i32 }
%struct.SIDEBOX = type { i32, i32 }
%struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*], %struct.SIDEBOX* }
%struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 }
%struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.termbox*, %struct.LOCBOX* }
@numcells = external global i32 ; <i32*> [#uses=1]
@cellarray = external global %struct.cellbox** ; <%struct.cellbox***> [#uses=1]
@numBinsY = external global i32 ; <i32*> [#uses=1]
define fastcc void @fixpenal() {
define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind {
entry:
%tmp491 = load i32* @numcells, align 4 ; <i32> [#uses=1]
%tmp9 = load %struct.cellbox*** @cellarray, align 4 ; <%struct.cellbox**> [#uses=1]
%tmp77.i = load i32* @numBinsY, align 4 ; <i32> [#uses=2]
br label %bb490
br i1 undef, label %smvp.exit, label %bb.i3
bb8: ; preds = %bb490, %cond_false428
%foo3 = phi i1 [ 0, %bb490 ], [ 1, %cond_false428 ]
br i1 %foo3, label %cond_false58.i, label %cond_false.i
bb.i3: ; preds = %bb.i3, %bb134
br i1 undef, label %smvp.exit, label %bb.i3
cond_false.i: ; preds = %bb8
ret void
smvp.exit: ; preds = %bb.i3
%0 = fmul double %d1, 2.400000e-03 ; <double> [#uses=2]
br i1 undef, label %bb138.preheader, label %bb159
cond_false58.i: ; preds = %bb8
%highBinX.0.i = select i1 false, i32 1, i32 0 ; <i32> [#uses=2]
br i1 %foo3, label %cond_next85.i, label %cond_false76.i
bb138.preheader: ; preds = %smvp.exit
br label %bb138
cond_false76.i: ; preds = %cond_false58.i
ret void
bb138: ; preds = %bb138, %bb138.preheader
br i1 undef, label %bb138, label %bb145.loopexit
cond_next85.i: ; preds = %cond_false58.i
br i1 %foo3, label %cond_next105.i, label %cond_false98.i
bb142: ; preds = %bb.nph218.bb.nph218.split_crit_edge, %phi0.exit
%1 = fmul double %d1, -1.200000e-03 ; <double> [#uses=1]
%2 = fadd double %d2, %1 ; <double> [#uses=1]
%3 = fmul double %2, %d2 ; <double> [#uses=1]
%4 = fsub double 0.000000e+00, %3 ; <double> [#uses=1]
br i1 %14, label %phi1.exit, label %bb.i35
cond_false98.i: ; preds = %cond_next85.i
ret void
bb.i35: ; preds = %bb142
%5 = call arm_apcscc double @sin(double %15) nounwind readonly ; <double> [#uses=1]
%6 = fmul double %5, 0x4031740AFA84AD8A ; <double> [#uses=1]
%7 = fsub double 1.000000e+00, undef ; <double> [#uses=1]
%8 = fdiv double %7, 6.000000e-01 ; <double> [#uses=1]
br label %phi1.exit
cond_next105.i: ; preds = %cond_next85.i
%tmp108.i = icmp eq i32 1, %highBinX.0.i ; <i1> [#uses=1]
%tmp115.i = icmp eq i32 1, %tmp77.i ; <i1> [#uses=1]
%bothcond.i = and i1 %tmp115.i, %tmp108.i ; <i1> [#uses=1]
%storemerge.i = select i1 %bothcond.i, i32 1, i32 0 ; <i32> [#uses=2]
br i1 %bothcond.i, label %whoOverlaps.exit, label %bb503.preheader.i
phi1.exit: ; preds = %bb.i35, %bb142
%.pn = phi double [ %6, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=0]
%9 = phi double [ %8, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=1]
%10 = fmul double undef, %9 ; <double> [#uses=0]
br i1 %14, label %phi0.exit, label %bb.i
bb503.preheader.i: ; preds = %bb513.i, %cond_next105.i
%i.022.0.i = phi i32 [ %tmp512.i, %bb513.i ], [ 0, %cond_next105.i ] ; <i32> [#uses=2]
%tmp165.i = getelementptr i32*** null, i32 %i.022.0.i ; <i32***> [#uses=0]
br label %bb503.i
bb.i: ; preds = %phi1.exit
unreachable
bb137.i: ; preds = %bb503.i
br i1 %tmp506.i, label %bb162.i, label %bb148.i
phi0.exit: ; preds = %phi1.exit
%11 = fsub double %4, undef ; <double> [#uses=1]
%12 = fadd double 0.000000e+00, %11 ; <double> [#uses=1]
store double %12, double* undef, align 4
br label %bb142
bb148.i: ; preds = %bb137.i
ret void
bb145.loopexit: ; preds = %bb138
br i1 undef, label %bb.nph218.bb.nph218.split_crit_edge, label %bb159
bb162.i: ; preds = %bb137.i
%tmp49435.i = load i32* null ; <i32> [#uses=1]
br label %bb170.i
bb.nph218.bb.nph218.split_crit_edge: ; preds = %bb145.loopexit
%13 = fmul double %0, 0x401921FB54442D18 ; <double> [#uses=1]
%14 = fcmp ugt double %0, 6.000000e-01 ; <i1> [#uses=2]
%15 = fdiv double %13, 6.000000e-01 ; <double> [#uses=1]
br label %bb142
bb170.i: ; preds = %bb491.i, %bb162.i
%indvar.i = phi i32 [ %k.032.0.i, %bb491.i ], [ 0, %bb162.i ] ; <i32> [#uses=2]
%k.032.0.i = add i32 %indvar.i, 1 ; <i32> [#uses=2]
%tmp173.i = getelementptr i32* null, i32 %k.032.0.i ; <i32*> [#uses=1]
%tmp174.i = load i32* %tmp173.i ; <i32> [#uses=4]
%tmp177.i = icmp eq i32 %tmp174.i, %cell.1 ; <i1> [#uses=1]
%tmp184.i = icmp sgt i32 %tmp174.i, %tmp491 ; <i1> [#uses=1]
%bothcond = or i1 %tmp177.i, %tmp184.i ; <i1> [#uses=1]
br i1 %bothcond, label %bb491.i, label %cond_next188.i
bb159: ; preds = %bb145.loopexit, %smvp.exit, %bb134
unreachable
cond_next188.i: ; preds = %bb170.i
%tmp191.i = getelementptr %struct.cellbox** %tmp9, i32 %tmp174.i ; <%struct.cellbox**> [#uses=1]
%tmp192.i = load %struct.cellbox** %tmp191.i ; <%struct.cellbox*> [#uses=1]
%tmp195.i = icmp eq i32 %tmp174.i, 0 ; <i1> [#uses=1]
br i1 %tmp195.i, label %bb491.i, label %cond_true198.i
cond_true198.i: ; preds = %cond_next188.i
%tmp210.i = getelementptr %struct.cellbox* %tmp192.i, i32 0, i32 3 ; <i32*> [#uses=0]
ret void
bb491.i: ; preds = %cond_next188.i, %bb170.i
%tmp490.i = add i32 %indvar.i, 2 ; <i32> [#uses=1]
%tmp496.i = icmp slt i32 %tmp49435.i, %tmp490.i ; <i1> [#uses=1]
br i1 %tmp496.i, label %bb500.i, label %bb170.i
bb500.i: ; preds = %bb491.i
%indvar.next82.i = add i32 %j.0.i, 1 ; <i32> [#uses=1]
br label %bb503.i
bb503.i: ; preds = %bb500.i, %bb503.preheader.i
%j.0.i = phi i32 [ 0, %bb503.preheader.i ], [ %indvar.next82.i, %bb500.i ] ; <i32> [#uses=2]
%tmp506.i = icmp sgt i32 %j.0.i, %tmp77.i ; <i1> [#uses=1]
br i1 %tmp506.i, label %bb513.i, label %bb137.i
bb513.i: ; preds = %bb503.i
%tmp512.i = add i32 %i.022.0.i, 1 ; <i32> [#uses=2]
%tmp516.i = icmp sgt i32 %tmp512.i, %highBinX.0.i ; <i1> [#uses=1]
br i1 %tmp516.i, label %whoOverlaps.exit, label %bb503.preheader.i
whoOverlaps.exit: ; preds = %bb513.i, %cond_next105.i
%foo = phi i1 [ 1, %bb513.i], [0, %cond_next105.i]
br i1 %foo, label %cond_false428, label %bb490
cond_false428: ; preds = %whoOverlaps.exit
br i1 %foo, label %bb497, label %bb8
bb490: ; preds = %whoOverlaps.exit, %entry
%binY.tmp.2 = phi i32 [ 0, %entry ], [ %storemerge.i, %whoOverlaps.exit ] ; <i32> [#uses=1]
%cell.1 = phi i32 [ 1, %entry ], [ 0, %whoOverlaps.exit ] ; <i32> [#uses=1]
%foo2 = phi i1 [ 1, %entry], [0, %whoOverlaps.exit]
br i1 %foo2, label %bb497, label %bb8
bb497: ; preds = %bb490, %cond_false428
%binY.tmp.3 = phi i32 [ %binY.tmp.2, %bb490 ], [ %storemerge.i, %cond_false428 ] ; <i32> [#uses=0]
ret void
bb166: ; preds = %bb127
unreachable
}
declare arm_apcscc double @sin(double) nounwind readonly

58
test/CodeGen/X86/2007-11-30-TestLoadFolding.ll
View File

@ -1,58 +0,0 @@
; RUN: llc < %s -march=x86 -stats |& \
; RUN: grep {1 .*folded into instructions}
; RUN: llc < %s -march=x86 | grep cmp | count 4
%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
define fastcc i32 @perimeter(%struct.quad_struct* %tree, i32 %size) {
entry:
%tree.idx7.val = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
%tmp8.i51 = icmp eq %struct.quad_struct* %tree.idx7.val, null ; <i1> [#uses=2]
br i1 %tmp8.i51, label %cond_next, label %cond_next.i52
cond_next.i52: ; preds = %entry
ret i32 0
cond_next: ; preds = %entry
%tmp59 = load i32* null, align 4 ; <i32> [#uses=1]
%tmp70 = icmp eq i32 %tmp59, 2 ; <i1> [#uses=1]
br i1 %tmp70, label %cond_true.i35, label %bb80
cond_true.i35: ; preds = %cond_next
%tmp14.i.i37 = load %struct.quad_struct** null, align 4 ; <%struct.quad_struct*> [#uses=1]
%tmp3.i160 = load i32* null, align 4 ; <i32> [#uses=1]
%tmp4.i161 = icmp eq i32 %tmp3.i160, 2 ; <i1> [#uses=1]
br i1 %tmp4.i161, label %cond_true.i163, label %cond_false.i178
cond_true.i163: ; preds = %cond_true.i35
%tmp7.i162 = sdiv i32 %size, 4 ; <i32> [#uses=2]
%tmp13.i168 = tail call fastcc i32 @sum_adjacent( %struct.quad_struct* null, i32 3, i32 2, i32 %tmp7.i162 ) ; <i32> [#uses=1]
%tmp18.i11.i170 = getelementptr %struct.quad_struct* %tmp14.i.i37, i32 0, i32 4 ; <%struct.quad_struct**> [#uses=1]
%tmp19.i12.i171 = load %struct.quad_struct** %tmp18.i11.i170, align 4 ; <%struct.quad_struct*> [#uses=1]
%tmp21.i173 = tail call fastcc i32 @sum_adjacent( %struct.quad_struct* %tmp19.i12.i171, i32 3, i32 2, i32 %tmp7.i162 ) ; <i32> [#uses=1]
%tmp22.i174 = add i32 %tmp21.i173, %tmp13.i168 ; <i32> [#uses=1]
br i1 %tmp4.i161, label %cond_true.i141, label %cond_false.i156
cond_false.i178: ; preds = %cond_true.i35
ret i32 0
cond_true.i141: ; preds = %cond_true.i163
%tmp7.i140 = sdiv i32 %size, 4 ; <i32> [#uses=1]
%tmp21.i151 = tail call fastcc i32 @sum_adjacent( %struct.quad_struct* null, i32 3, i32 2, i32 %tmp7.i140 ) ; <i32> [#uses=0]
ret i32 0
cond_false.i156: ; preds = %cond_true.i163
%tmp22.i44 = add i32 0, %tmp22.i174 ; <i32> [#uses=0]
br i1 %tmp8.i51, label %bb22.i, label %cond_next.i
bb80: ; preds = %cond_next
ret i32 0
cond_next.i: ; preds = %cond_false.i156
ret i32 0
bb22.i: ; preds = %cond_false.i156
ret i32 0
}
declare fastcc i32 @sum_adjacent(%struct.quad_struct*, i32, i32, i32)

1
test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
View File

@ -13,7 +13,6 @@ define i32 @t(i32 %clientPort, i32 %pluginID, i32 %requestID, i32 %objectID, i64
entry:
; CHECK: _t:
; CHECK: movl 16(%rbp),
; CHECK: movl 16(%rbp), %edx
%0 = zext i32 %argumentsLength to i64 ; <i64> [#uses=1]
%1 = zext i32 %clientPort to i64 ; <i64> [#uses=1]
%2 = inttoptr i64 %1 to %struct.ComplexType* ; <%struct.ComplexType*> [#uses=1]

2
test/CodeGen/X86/twoaddr-delete.ll → test/CodeGen/X86/codegen-dce.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -stats |& grep {twoaddrinstr} | grep {Number of dead instructions deleted}
; RUN: llc < %s -march=x86 -stats |& grep {codegen-dce} | grep {Number of dead instructions deleted}
%struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] }
%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* }

9
test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
View File

@ -1,19 +1,20 @@
; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \
; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 5
; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 10
; RUN: grep {leal 1(\%rsi),} %t
define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2) nounwind optsize {
define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize {
entry:
%0 = add i32 %i2, 1 ; <i32> [#uses=1]
%1 = sext i32 %0 to i64 ; <i64> [#uses=1]
%2 = getelementptr i8* null, i64 %1 ; <i8*> [#uses=1]
%2 = getelementptr i8* %ptr, i64 %1 ; <i8*> [#uses=1]
%3 = load i8* %2, align 1 ; <i8> [#uses=1]
%4 = icmp eq i8 0, %3 ; <i1> [#uses=1]
br i1 %4, label %bb3, label %bb34
bb3: ; preds = %entry
%5 = add i32 %i2, 4 ; <i32> [#uses=0]
ret i8 0
%6 = trunc i32 %5 to i8
ret i8 %6
bb34: ; preds = %entry
ret i8 0

2
test/CodeGen/X86/ins_subreg_coalesce-3.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 | grep mov | count 11
; RUN: llc < %s -march=x86-64 | grep mov | count 5
%struct.COMPOSITE = type { i8, i16, i16 }
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }

4
test/CodeGen/X86/sext-i1.ll
View File

@ -44,9 +44,9 @@ entry:
; 64: t3:
; 64: cmpl $1
; 64: sbbl
; 64: cmpl
; 64: sbbq
; 64: cmpq
; 64: xorl
%not.tobool = icmp eq i32 undef, 0 ; <i1> [#uses=2]
%cond = sext i1 %not.tobool to i32 ; <i32> [#uses=1]
%conv = sext i1 %not.tobool to i64 ; <i64> [#uses=1]

6
test/CodeGen/X86/sse3.ll
View File

@ -63,10 +63,10 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
ret <8 x i16> %tmp
; X64: t4:
; X64: pextrw $7, %xmm0, %eax
; X64: pshufhw $100, %xmm0, %xmm1
; X64: pinsrw $1, %eax, %xmm1
; X64: pshufhw $100, %xmm0, %xmm2
; X64: pinsrw $1, %eax, %xmm2
; X64: pextrw $1, %xmm0, %eax
; X64: movaps %xmm1, %xmm0
; X64: movaps %xmm2, %xmm0
; X64: pinsrw $4, %eax, %xmm0
; X64: ret
}

2
test/CodeGen/X86/tailcall2.ll
View File

@ -147,6 +147,8 @@ define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
; 32: t11:
; 32-NOT: subl ${{[0-9]+}}, %esp
; 32: jne
; 32-NOT: movl
; 32-NOT: addl ${{[0-9]+}}, %esp
; 32: jmp {{_?}}foo5