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Use BuildMI more, Create*Instruction less

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5291 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2003-01-15 17:47:49 +00:00
parent 73df3bfb68
commit 00dca91658
3 changed files with 71 additions and 135 deletions
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38
lib/Target/SparcV9/SparcV9InstrInfo.cpp
View File

@@ -53,7 +53,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
// Set the high 22 bits in dest if non-zero and simm13 field of OR not enough // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
{ {
miSETHI = Create2OperandInstr_UImmed(SETHI, C, dest); miSETHI = BuildMI(SETHI, 2).addZImm(C).addRegDef(dest);
miSETHI->setOperandHi32(0); miSETHI->setOperandHi32(0);
mvec.push_back(miSETHI); mvec.push_back(miSETHI);
} }
@@ -64,7 +64,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
{ {
if (miSETHI) if (miSETHI)
{ // unsigned value with high-order bits set using SETHI { // unsigned value with high-order bits set using SETHI
miOR = BuildMI(OR, 3).addReg(dest).addZImm(C).addReg(dest, MOTy::Def); miOR = BuildMI(OR, 3).addReg(dest).addZImm(C).addRegDef(dest);
miOR->setOperandLo32(1); miOR->setOperandLo32(1);
} }
else else
@@ -103,8 +103,7 @@ CreateSETSWConst(const TargetMachine& target, int32_t C,
// Sign-extend to the high 32 bits if needed // Sign-extend to the high 32 bits if needed
if (C < 0 && (-C) > (int32_t) MAXSIMM) if (C < 0 && (-C) > (int32_t) MAXSIMM)
mvec.push_back(BuildMI(SRA, 3).addReg(dest).addZImm(0).addReg(dest, mvec.push_back(BuildMI(SRA, 3).addReg(dest).addZImm(0).addRegDef(dest));
MOTy::Def));
} }
@@ -131,15 +130,13 @@ CreateSETXConst(const TargetMachine& target, uint64_t C,
CreateSETUWConst(target, (C >> 32), tmpReg, mvec); CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
// Shift tmpReg left by 32 bits // Shift tmpReg left by 32 bits
mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addReg(tmpReg, mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addRegDef(tmpReg));
MOTy::Def));
// Code to set the low 32 bits of the value in register `dest' // Code to set the low 32 bits of the value in register `dest'
CreateSETUWConst(target, C, dest, mvec); CreateSETUWConst(target, C, dest, mvec);
// dest = OR(tmpReg, dest) // dest = OR(tmpReg, dest)
mvec.push_back(BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addReg(dest, mvec.push_back(BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest));
MOTy::Def));
} }
@@ -156,12 +153,12 @@ CreateSETUWLabel(const TargetMachine& target, Value* val,
MachineInstr* MI; MachineInstr* MI;
// Set the high 22 bits in dest // Set the high 22 bits in dest
MI = Create2OperandInstr(SETHI, val, dest); MI = BuildMI(SETHI, 2).addReg(val).addRegDef(dest);
MI->setOperandHi32(0); MI->setOperandHi32(0);
mvec.push_back(MI); mvec.push_back(MI);
// Set the low 10 bits in dest // Set the low 10 bits in dest
MI = BuildMI(OR, 3).addReg(dest).addReg(val).addReg(dest, MOTy::Def); MI = BuildMI(OR, 3).addReg(dest).addReg(val).addRegDef(dest);
MI->setOperandLo32(1); MI->setOperandLo32(1);
mvec.push_back(MI); mvec.push_back(MI);
} }
@@ -183,24 +180,23 @@ CreateSETXLabel(const TargetMachine& target,
MachineInstr* MI; MachineInstr* MI;
MI = Create2OperandInstr_Addr(SETHI, val, tmpReg); MI = BuildMI(SETHI, 2).addReg(val).addRegDef(tmpReg);
MI->setOperandHi64(0); MI->setOperandHi64(0);
mvec.push_back(MI); mvec.push_back(MI);
MI = BuildMI(OR, 3).addReg(tmpReg).addPCDisp(val).addReg(tmpReg, MOTy::Def); MI = BuildMI(OR, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
MI->setOperandLo64(1); MI->setOperandLo64(1);
mvec.push_back(MI); mvec.push_back(MI);
mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addReg(tmpReg, mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addRegDef(tmpReg));
MOTy::Def)); MI = BuildMI(SETHI, 2).addPCDisp(val).addRegDef(dest);
MI = Create2OperandInstr_Addr(SETHI, val, dest);
MI->setOperandHi32(0); MI->setOperandHi32(0);
mvec.push_back(MI); mvec.push_back(MI);
MI = BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addReg(dest, MOTy::Def); MI = BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
mvec.push_back(MI); mvec.push_back(MI);
MI = BuildMI(OR, 3).addReg(dest).addPCDisp(val).addReg(dest, MOTy::Def); MI = BuildMI(OR, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
MI->setOperandLo32(1); MI->setOperandLo32(1);
mvec.push_back(MI); mvec.push_back(MI);
} }
@@ -454,7 +450,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
unsigned Opcode = ChooseLoadInstruction(val->getType()); unsigned Opcode = ChooseLoadInstruction(val->getType());
mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg). mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
addSImm(zeroOffset).addReg(dest, MOTy::Def)); addSImm(zeroOffset).addRegDef(dest));
// Make sure constant is emitted to constant pool in assembly code. // Make sure constant is emitted to constant pool in assembly code.
MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val)); MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
@@ -628,7 +624,7 @@ UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
const Type* Ty =isa<PointerType>(resultType) ? Type::ULongTy : resultType; const Type* Ty =isa<PointerType>(resultType) ? Type::ULongTy : resultType;
MachineInstr* MI = MachineInstr* MI =
BuildMI(opCode, 3).addReg(Constant::getNullValue(Ty)) BuildMI(opCode, 3).addReg(Constant::getNullValue(Ty))
.addReg(src).addReg(dest, MOTy::Def); .addReg(src).addRegDef(dest);
mvec.push_back(MI); mvec.push_back(MI);
} }
} }
@@ -656,12 +652,12 @@ CreateBitExtensionInstructions(bool signExtend,
srcVal, destVal, "make32"); srcVal, destVal, "make32");
mcfi.addTemp(tmpI); mcfi.addTemp(tmpI);
mvec.push_back(BuildMI(SLLX, 3).addReg(srcVal).addZImm(32-numLowBits) mvec.push_back(BuildMI(SLLX, 3).addReg(srcVal).addZImm(32-numLowBits)
.addReg(tmpI, MOTy::Def)); .addRegDef(tmpI));
srcVal = tmpI; srcVal = tmpI;
} }
mvec.push_back(BuildMI(signExtend? SRA : SRL, 3).addReg(srcVal) mvec.push_back(BuildMI(signExtend? SRA : SRL, 3).addReg(srcVal)
.addZImm(32-numLowBits).addReg(destVal, MOTy::Def)); .addZImm(32-numLowBits).addRegDef(destVal));
} }

54
lib/Target/SparcV9/SparcV9InstrSelection.cpp
View File

@@ -303,11 +303,7 @@ CreateConvertFPToIntInstr(Type::PrimitiveID destTID,
{ {
MachineOpCode opCode = ChooseConvertFPToIntInstr(destTID, srcVal->getType()); MachineOpCode opCode = ChooseConvertFPToIntInstr(destTID, srcVal->getType());
assert(opCode != INVALID_OPCODE && "Expected to need conversion!"); assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
return BuildMI(opCode, 2).addReg(srcVal).addRegDef(destVal);
MachineInstr* M = new MachineInstr(opCode);
M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, srcVal);
M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, destVal);
return M;
} }
// CreateCodeToConvertFloatToInt: Convert FP value to signed or unsigned integer // CreateCodeToConvertFloatToInt: Convert FP value to signed or unsigned integer
@@ -367,13 +363,9 @@ static inline MachineInstr*
CreateMovFloatInstruction(const InstructionNode* instrNode, CreateMovFloatInstruction(const InstructionNode* instrNode,
const Type* resultType) const Type* resultType)
{ {
MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy) return BuildMI((resultType == Type::FloatTy) ? FMOVS : FMOVD, 2)
? FMOVS : FMOVD); .addReg(instrNode->leftChild()->getValue())
minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, .addRegDef(instrNode->getValue());
instrNode->leftChild()->getValue());
minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
instrNode->getValue());
return minstr;
} }
static inline MachineInstr* static inline MachineInstr*
@@ -501,11 +493,8 @@ static inline MachineInstr*
CreateIntNegInstruction(const TargetMachine& target, CreateIntNegInstruction(const TargetMachine& target,
Value* vreg) Value* vreg)
{ {
MachineInstr* minstr = new MachineInstr(SUB); return BuildMI(SUB, 3).addMReg(target.getRegInfo().getZeroRegNum())
minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum()); .addReg(vreg).addRegDef(vreg);
minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg);
minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg);
return minstr;
} }
@@ -600,13 +589,14 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
C = -C; C = -C;
} }
if (C == 0 || C == 1) if (C == 0 || C == 1) {
{
cost = target.getInstrInfo().minLatency(ADD); cost = target.getInstrInfo().minLatency(ADD);
unsigned ZeroReg = target.getRegInfo().getZeroRegNum(); unsigned Zero = target.getRegInfo().getZeroRegNum();
MachineInstr* M = (C == 0) MachineInstr* M;
? Create3OperandInstr_Reg(ADD, ZeroReg, ZeroReg, destVal) if (C == 0)
: Create3OperandInstr_Reg(ADD, lval, ZeroReg, destVal); M = BuildMI(ADD,3).addMReg(Zero).addMReg(Zero).addRegDef(destVal);
else
M = BuildMI(ADD,3).addReg(lval).addMReg(Zero).addRegDef(destVal);
mvec.push_back(M); mvec.push_back(M);
} }
else if (isPowerOf2(C, pow)) else if (isPowerOf2(C, pow))
@@ -634,8 +624,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
MachineOpCode opCode = (dval < 0) MachineOpCode opCode = (dval < 0)
? (resultType == Type::FloatTy? FNEGS : FNEGD) ? (resultType == Type::FloatTy? FNEGS : FNEGD)
: (resultType == Type::FloatTy? FMOVS : FMOVD); : (resultType == Type::FloatTy? FMOVS : FMOVD);
MachineInstr* M = Create2OperandInstr(opCode, lval, destVal); mvec.push_back(BuildMI(opCode,2).addReg(lval).addRegDef(destVal));
mvec.push_back(M);
} }
} }
} }
@@ -695,11 +684,8 @@ CreateMulInstruction(const TargetMachine &target, Function* F,
MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE) MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
? forceMulOp ? forceMulOp
: ChooseMulInstructionByType(destVal->getType())); : ChooseMulInstructionByType(destVal->getType()));
MachineInstr* M = new MachineInstr(mulOp); mvec.push_back(BuildMI(mulOp, 3).addReg(lval).addReg(rval)
M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval); .addRegDef(destVal));
M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval);
M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal);
mvec.push_back(M);
} }
} }
@@ -1438,9 +1424,9 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
{ // First find the unary operand. It may be left or right, usually right. { // First find the unary operand. It may be left or right, usually right.
Value* notArg = BinaryOperator::getNotArgument( Value* notArg = BinaryOperator::getNotArgument(
cast<BinaryOperator>(subtreeRoot->getInstruction())); cast<BinaryOperator>(subtreeRoot->getInstruction()));
mvec.push_back(Create3OperandInstr_Reg(XNOR, notArg, unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
target.getRegInfo().getZeroRegNum(), mvec.push_back(BuildMI(XNOR, 3).addReg(notArg).addMReg(ZeroReg)
subtreeRoot->getValue())); .addRegDef(subtreeRoot->getValue()));
break; break;
} }
@@ -2010,7 +1996,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
// Use JMPL for indirect calls. // Use JMPL for indirect calls.
// //
if (isa<Function>(callee)) // direct function call if (isa<Function>(callee)) // direct function call
M = Create1OperandInstr_Addr(CALL, callee); M = BuildMI(CALL, 1).addPCDisp(callee);
else // indirect function call else // indirect function call
M = BuildMI(JMPLCALL, M = BuildMI(JMPLCALL,
3).addReg(callee).addSImm((int64_t)0).addReg(retAddrReg); 3).addReg(callee).addSImm((int64_t)0).addReg(retAddrReg);

106
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@@ -12,7 +12,7 @@
#include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/InstrSelectionSupport.h" #include "llvm/CodeGen/InstrSelectionSupport.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineInstrAnnot.h" #include "llvm/CodeGen/MachineInstrAnnot.h"
#include "llvm/CodeGen/RegAllocCommon.h" #include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/FunctionLiveVarInfo.h" // FIXME: Remove #include "llvm/CodeGen/FunctionLiveVarInfo.h" // FIXME: Remove
@@ -1100,14 +1100,14 @@ UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
if (getRegType(DestReg) == IntRegType) if (getRegType(DestReg) == IntRegType)
{ // copy intCC reg to int reg { // copy intCC reg to int reg
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg); MI = BuildMI(RDCCR, 2).addMReg(SrcReg+1).addMReg(DestReg, MOTy::Def);
} }
else else
{ // copy int reg to intCC reg { // copy int reg to intCC reg
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
assert(getRegType(SrcReg) == IntRegType assert(getRegType(SrcReg) == IntRegType
&& "Can only copy CC reg to/from integer reg"); && "Can only copy CC reg to/from integer reg");
MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1); MI = BuildMI(WRCCR, 2).addMReg(SrcReg).addMReg(DestReg+1, MOTy::Def);
} }
break; break;
@@ -1116,15 +1116,16 @@ UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
break; break;
case IntRegType: case IntRegType:
MI = Create3OperandInstr_Reg(ADD, SrcReg, getZeroRegNum(), DestReg); MI = BuildMI(ADD, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
.addMReg(DestReg, MOTy::Def);
break; break;
case FPSingleRegType: case FPSingleRegType:
MI = Create2OperandInstr_Reg(FMOVS, SrcReg, DestReg); MI = BuildMI(FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
break; break;
case FPDoubleRegType: case FPDoubleRegType:
MI = Create2OperandInstr_Reg(FMOVD, SrcReg, DestReg); MI = BuildMI(FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
break; break;
default: default:
@@ -1152,32 +1153,17 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
switch (RegType) { switch (RegType) {
case IntRegType: case IntRegType:
assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset)); assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset));
MI = new MachineInstr(STX, 3); MI = BuildMI(STX, 3).addMReg(SrcReg).addMReg(DestPtrReg).addSImm(Offset);
MI->SetMachineOperandReg(0, SrcReg);
MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
break; break;
case FPSingleRegType: case FPSingleRegType:
assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset)); assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset));
MI = new MachineInstr(ST, 3); MI = BuildMI(ST, 3).addMReg(SrcReg).addMReg(DestPtrReg).addSImm(Offset);
MI->SetMachineOperandReg(0, SrcReg);
MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
break; break;
case FPDoubleRegType: case FPDoubleRegType:
assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset)); assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset));
MI = new MachineInstr(STD, 3); MI = BuildMI(STD, 3).addMReg(SrcReg).addMReg(DestPtrReg).addSImm(Offset);
MI->SetMachineOperandReg(0, SrcReg);
MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
break; break;
case IntCCRegType: case IntCCRegType:
@@ -1185,26 +1171,22 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg); MI = BuildMI(RDCCR, 2).addMReg(SrcReg+1).addMReg(scratchReg, MOTy::Def);
mvec.push_back(MI); mvec.push_back(MI);
cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType); cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
break; return;
case FloatCCRegType: case FloatCCRegType:
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here"); assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset)); assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset));
MI = new MachineInstr(STXFSR, 3); MI = BuildMI(STXFSR, 3).addMReg(SrcReg).addMReg(DestPtrReg).addSImm(Offset);
MI->SetMachineOperandReg(0, SrcReg);
MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
break; break;
default: default:
assert(0 && "Unknown RegType in cpReg2MemMI"); assert(0 && "Unknown RegType in cpReg2MemMI");
} }
mvec.push_back(MI);
} }
@@ -1225,32 +1207,20 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
switch (RegType) { switch (RegType) {
case IntRegType: case IntRegType:
assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset)); assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset));
MI = new MachineInstr(LDX, 3); MI = BuildMI(LDX, 3).addMReg(SrcPtrReg).addSImm(Offset)
MI->SetMachineOperandReg(0, SrcPtrReg); .addMReg(DestReg, MOTy::Def);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
mvec.push_back(MI);
break; break;
case FPSingleRegType: case FPSingleRegType:
assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset)); assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset));
MI = new MachineInstr(LD, 3); MI = BuildMI(LD, 3).addMReg(SrcPtrReg).addSImm(Offset)
MI->SetMachineOperandReg(0, SrcPtrReg); .addMReg(DestReg, MOTy::Def);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
mvec.push_back(MI);
break; break;
case FPDoubleRegType: case FPDoubleRegType:
assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset)); assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset));
MI = new MachineInstr(LDD, 3); MI = BuildMI(LDD, 3).addMReg(SrcPtrReg).addSImm(Offset).addMReg(DestReg,
MI->SetMachineOperandReg(0, SrcPtrReg); MOTy::Def);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
mvec.push_back(MI);
break; break;
case IntCCRegType: case IntCCRegType:
@@ -1259,25 +1229,21 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType); cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1); MI = BuildMI(WRCCR, 2).addMReg(scratchReg).addMReg(DestReg+1, MOTy::Def);
mvec.push_back(MI);
break; break;
case FloatCCRegType: case FloatCCRegType:
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here"); assert(0 && "Tell Vikram if this assertion fails: we may have to mask "
"out the other bits here");
assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset)); assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset));
MI = new MachineInstr(LDXFSR, 3); MI = BuildMI(LDXFSR, 3).addMReg(SrcPtrReg).addSImm(Offset)
MI->SetMachineOperandReg(0, SrcPtrReg); .addMReg(DestReg, MOTy::Def);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
mvec.push_back(MI);
break; break;
default: default:
assert(0 && "Unknown RegType in cpMem2RegMI"); assert(0 && "Unknown RegType in cpMem2RegMI");
} }
mvec.push_back(MI);
} }
@@ -1288,8 +1254,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
void void
UltraSparcRegInfo::cpValue2Value(Value *Src, UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
Value *Dest,
vector<MachineInstr*>& mvec) const { vector<MachineInstr*>& mvec) const {
int RegType = getRegType( Src ); int RegType = getRegType( Src );
@@ -1299,25 +1264,14 @@ UltraSparcRegInfo::cpValue2Value(Value *Src,
switch( RegType ) { switch( RegType ) {
case IntRegType: case IntRegType:
MI = new MachineInstr(ADD, 3); MI = BuildMI(ADD, 3).addReg(Src).addMReg(getZeroRegNum()).addRegDef(Dest);
MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
MI->SetMachineOperandReg(1, getZeroRegNum());
MI->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, Dest, true);
break; break;
case FPSingleRegType: case FPSingleRegType:
MI = new MachineInstr(FMOVS, 2); MI = BuildMI(FMOVS, 2).addReg(Src).addRegDef(Dest);
MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
break; break;
case FPDoubleRegType: case FPDoubleRegType:
MI = new MachineInstr(FMOVD, 2); MI = BuildMI(FMOVD, 2).addReg(Src).addRegDef(Dest);
MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
break; break;
default: default:
assert(0 && "Unknow RegType in CpValu2Value"); assert(0 && "Unknow RegType in CpValu2Value");
} }