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[SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words

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As the comment says, we always want to use STOC for 32-bit stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191767 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-10-01 14:33:55 +00:00
parent bba9390fc6
commit 00f5335ea0
3 changed files with 54 additions and 6 deletions
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8
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -2893,6 +2893,14 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
case SystemZ::SelectF128: case SystemZ::SelectF128:
return emitSelect(MI, MBB); return emitSelect(MI, MBB);
case SystemZ::CondStore8Mux:
return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
case SystemZ::CondStore8MuxInv:
return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
case SystemZ::CondStore16Mux:
return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
case SystemZ::CondStore16MuxInv:
return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
case SystemZ::CondStore8: case SystemZ::CondStore8:
return emitCondStore(MI, MBB, SystemZ::STC, 0, false); return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
case SystemZ::CondStore8Inv: case SystemZ::CondStore8Inv:

20
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -202,12 +202,20 @@ def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
def Select32 : SelectWrapper<GR32>; def Select32 : SelectWrapper<GR32>;
def Select64 : SelectWrapper<GR64>; def Select64 : SelectWrapper<GR64>;
defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, // We don't define 32-bit Mux stores because the low-only STOC should
nonvolatile_anyextloadi8, bdxaddr20only>; // always be used if possible.
defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8,
nonvolatile_anyextloadi16, bdxaddr20only>; nonvolatile_anyextloadi8, bdxaddr20only>,
defm CondStore32 : CondStores<GR32, nonvolatile_store, Requires<[FeatureHighWord]>;
nonvolatile_load, bdxaddr20only>; defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
nonvolatile_anyextloadi16, bdxaddr20only>,
Requires<[FeatureHighWord]>;
defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8,
nonvolatile_anyextloadi8, bdxaddr20only>;
defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,
nonvolatile_anyextloadi16, bdxaddr20only>;
defm CondStore32 : CondStores<GR32, nonvolatile_store,
nonvolatile_load, bdxaddr20only>;
defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
nonvolatile_anyextloadi8, bdxaddr20only>; nonvolatile_anyextloadi8, bdxaddr20only>;

32
test/CodeGen/SystemZ/fp-move-09.ll
View File

@ -28,3 +28,35 @@ define void @f2(float %val, i8 *%ptr) {
store i8 %trunc, i8 *%ptr store i8 %trunc, i8 *%ptr
ret void ret void
} }
; Like f2, but with a conditional store.
define void @f3(float %val, i8 *%ptr, i32 %which) {
; CHECK-LABEL: f3:
; CHECK: cijlh %r3, 0,
; CHECK: lgdr [[REG:%r[0-5]]], %f0
; CHECK: stch [[REG]], 0(%r2)
; CHECK: br %r14
%int = bitcast float %val to i32
%trunc = trunc i32 %int to i8
%old = load i8 *%ptr
%cmp = icmp eq i32 %which, 0
%res = select i1 %cmp, i8 %trunc, i8 %old
store i8 %res, i8 *%ptr
ret void
}
; ...and again with 16-bit memory.
define void @f4(float %val, i16 *%ptr, i32 %which) {
; CHECK-LABEL: f4:
; CHECK: cijlh %r3, 0,
; CHECK: lgdr [[REG:%r[0-5]]], %f0
; CHECK: sthh [[REG]], 0(%r2)
; CHECK: br %r14
%int = bitcast float %val to i32
%trunc = trunc i32 %int to i16
%old = load i16 *%ptr
%cmp = icmp eq i32 %which, 0
%res = select i1 %cmp, i16 %trunc, i16 %old
store i16 %res, i16 *%ptr
ret void
}